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[RISCV] Enable alias analysis by default
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In llvm alias analysis is off by default now.
This patch enable alias analysis on RISCV target during code generation by default,
and this makes more chances for improving performance.
Modified related test cases.

Differential Revision: https://reviews.llvm.org/D157250
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@Yunzezhu94
Yunzezhu94 committed Aug 10, 2023
1 parent 363b655 commit 5f73d2b
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Showing 5 changed files with 36 additions and 15 deletions.
7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSubtarget.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ static cl::opt<unsigned> RISCVMaxBuildIntsCost(
cl::desc("The maximum cost used for building integers."), cl::init(0),
cl::Hidden);

static cl::opt<bool> UseAA("riscv-use-aa", cl::init(true),
cl::desc("Enable the use of AA during codegen."));

void RISCVSubtarget::anchor() {}

RISCVSubtarget &
Expand Down Expand Up @@ -175,3 +178,7 @@ void RISCVSubtarget::getPostRAMutations(
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
Mutations.push_back(createRISCVMacroFusionDAGMutation());
}

/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
bool RISCVSubtarget::useAA() const { return UseAA; }
2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -220,6 +220,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {

void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
&Mutations) const override;

bool useAA() const override;
};
} // End llvm namespace

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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -15,15 +15,15 @@ define <vscale x 1 x double> @test(%struct.test* %addr, i64 %vl) {
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: addi a2, a0, 8
; CHECK-NEXT: vl1re64.v v8, (a2)
; CHECK-NEXT: vl1re64.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 8
; CHECK-NEXT: vl1re64.v v9, (a0)
; CHECK-NEXT: addi a0, sp, 24
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: addi a2, sp, 24
; CHECK-NEXT: vs1r.v v9, (a2)
; CHECK-NEXT: vl1re64.v v8, (a0)
; CHECK-NEXT: vl1re64.v v9, (a2)
; CHECK-NEXT: vl1re64.v v8, (a2)
; CHECK-NEXT: vl1re64.v v9, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v8, v9, v8
; CHECK-NEXT: csrrs a0, vlenb, zero
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12 changes: 12 additions & 0 deletions llvm/test/CodeGen/RISCV/vararg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -495,6 +495,8 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 20
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 35
Expand All @@ -517,6 +519,8 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 19
Expand All @@ -538,6 +542,8 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 20
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 35
Expand Down Expand Up @@ -804,6 +810,8 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 12
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: addi a3, sp, 27
Expand All @@ -828,6 +836,8 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: addi a3, s0, 19
Expand All @@ -851,6 +861,8 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 12
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 19
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, sp, 27
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18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -85,23 +85,23 @@ define void @foo4(ptr %p) nounwind {
; RV32ZDINX-LABEL: foo4:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: addi sp, sp, -16
; RV32ZDINX-NEXT: addi a1, a0, 2047
; RV32ZDINX-NEXT: lw a2, -3(a1)
; RV32ZDINX-NEXT: lw a3, 1(a1)
; RV32ZDINX-NEXT: sw a0, 8(sp)
; RV32ZDINX-NEXT: addi a0, a0, 2047
; RV32ZDINX-NEXT: lw a1, 1(a0)
; RV32ZDINX-NEXT: lw a0, -3(a0)
; RV32ZDINX-NEXT: lui a2, %hi(d)
; RV32ZDINX-NEXT: sw a0, %lo(d)(a2)
; RV32ZDINX-NEXT: sw a1, %lo(d+4)(a2)
; RV32ZDINX-NEXT: lui a0, %hi(d)
; RV32ZDINX-NEXT: sw a2, %lo(d)(a0)
; RV32ZDINX-NEXT: sw a3, %lo(d+4)(a0)
; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: foo4:
; RV64ZDINX: # %bb.0: # %entry
; RV64ZDINX-NEXT: addi sp, sp, -16
; RV64ZDINX-NEXT: ld a1, 2044(a0)
; RV64ZDINX-NEXT: sd a0, 8(sp)
; RV64ZDINX-NEXT: ld a0, 2044(a0)
; RV64ZDINX-NEXT: lui a1, %hi(d)
; RV64ZDINX-NEXT: sd a0, %lo(d)(a1)
; RV64ZDINX-NEXT: lui a0, %hi(d)
; RV64ZDINX-NEXT: sd a1, %lo(d)(a0)
; RV64ZDINX-NEXT: addi sp, sp, 16
; RV64ZDINX-NEXT: ret
entry:
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