Commits on Oct 8, 2024

1. [AMDGPU] Include WWM register spill into BB Prolog …

   With llvm#93526 we split the regalloc pipeline further
   to have a standalone allocation for wwm registers
   and per-lane VGPRs. Currently the presence of the
   wwm-spill reloads inserted at the bb-top limits the
   isBasicPrologue function during the per-lane vgpr
   regalloc to skip past the exec manipulation instruction
   and ended up causing incorrect codegen. The wmm-spill
   inserted during the wwm-regalloc pipeline should also
   be included in the bb-prolog so that the per-lane vgpr
   regalloc pipeline can identify the appropriate insertion
   points for their spills and copies.

   

   cdevadas committed Oct 8, 2024
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