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CodeGen: Remove redundant REQUIRES registered-target from tests #111982

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Oct 11, 2024
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CodeGen: Remove redundant REQUIRES registered-target from tests #111982

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1 change: 0 additions & 1 deletion llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-linux -run-pass=twoaddressinstruction -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64-unknown-linux --passes=two-address-instruction -verify-each %s -o - | FileCheck %s
# REQUIRES: aarch64-registered-target

# Verify that the register class is correctly constrained after the twoaddress replacement
---
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1 change: 0 additions & 1 deletion llvm/test/CodeGen/AMDGPU/expand-variadic-call.ll
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@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --function-signature
; RUN: opt -S --passes=expand-variadics --expand-variadics-override=lowering < %s | FileCheck %s
; REQUIRES: amdgpu-registered-target
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
target triple = "amdgcn-amd-amdhsa"

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1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/tls-align.ll
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@@ -1,4 +1,3 @@
; REQUIRES: x86-registered-target
; RUN: opt -passes=instcombine -S < %s | FileCheck %s

%class.Arr = type <{ [160 x %class.Derived], i32, [4 x i8] }>
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