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// Copyright lowRISC contributors. | ||
// Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
// SPDX-License-Identifier: Apache-2.0 | ||
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module clkgen_pynqz2 ( | ||
input IO_CLK, | ||
input IO_RST_N, | ||
output clk_sys, | ||
output rst_sys_n | ||
); | ||
logic locked_pll; | ||
logic io_clk_buf; | ||
logic clk_50_buf; | ||
logic clk_50_unbuf; | ||
logic clk_fb_buf; | ||
logic clk_fb_unbuf; | ||
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// input buffer | ||
IBUF io_clk_ibuf( | ||
.I (IO_CLK), | ||
.O (io_clk_buf) | ||
); | ||
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PLLE2_ADV #( | ||
.BANDWIDTH ("OPTIMIZED"), | ||
.COMPENSATION ("ZHOLD"), | ||
.STARTUP_WAIT ("FALSE"), | ||
.DIVCLK_DIVIDE (5), | ||
.CLKFBOUT_MULT (34), | ||
.CLKFBOUT_PHASE (0.000), | ||
.CLKOUT0_DIVIDE (17), | ||
.CLKOUT0_PHASE (0.000), | ||
.CLKOUT0_DUTY_CYCLE (0.500), | ||
.CLKIN1_PERIOD (8.000) | ||
) pll ( | ||
.CLKFBOUT (clk_fb_unbuf), | ||
.CLKOUT0 (clk_50_unbuf), | ||
.CLKOUT1 (), | ||
.CLKOUT2 (), | ||
.CLKOUT3 (), | ||
.CLKOUT4 (), | ||
.CLKOUT5 (), | ||
// Input clock control | ||
.CLKFBIN (clk_fb_buf), | ||
.CLKIN1 (io_clk_buf), | ||
.CLKIN2 (1'b0), | ||
// Tied to always select the primary input clock | ||
.CLKINSEL (1'b1), | ||
// Ports for dynamic reconfiguration | ||
.DADDR (7'h0), | ||
.DCLK (1'b0), | ||
.DEN (1'b0), | ||
.DI (16'h0), | ||
.DO (), | ||
.DRDY (), | ||
.DWE (1'b0), | ||
// Other control and status signals | ||
.LOCKED (locked_pll), | ||
.PWRDWN (1'b0), | ||
// Do not reset PLL on external reset, otherwise ILA disconnects at a reset | ||
.RST (1'b0)); | ||
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// output buffering | ||
BUFG clk_fb_bufg ( | ||
.I (clk_fb_unbuf), | ||
.O (clk_fb_buf) | ||
); | ||
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BUFG clk_50_bufg ( | ||
.I (clk_50_unbuf), | ||
.O (clk_50_buf) | ||
); | ||
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// outputs | ||
// clock | ||
assign clk_sys = clk_50_buf; | ||
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// reset | ||
assign rst_sys_n = locked_pll & IO_RST_N; | ||
endmodule |
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// Copyright lowRISC contributors. | ||
// Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
// SPDX-License-Identifier: Apache-2.0 | ||
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// This is the top level SystemVerilog file that connects the IO on the board to the Ibex Demo System. | ||
module top_pynqz2 ( | ||
// These inputs are defined in data/pins_pynqz2.xdc | ||
input IO_CLK, | ||
input IO_RST, | ||
input [1:0] SW, | ||
input [2:0] BTN, | ||
output [3:0] LED, | ||
output [3:0] GPIOS, | ||
output [5:0] RGB_LED, | ||
input UART_RX, | ||
output UART_TX, | ||
input SPI_RX, | ||
output SPI_TX, | ||
output SPI_SCK | ||
); | ||
parameter SRAMInitFile = ""; | ||
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logic clk_sys, rst_sys_n; | ||
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// Instantiating the Ibex Demo System. | ||
ibex_demo_system #( | ||
.GpiWidth(5), | ||
.GpoWidth(8), | ||
.PwmWidth(6), | ||
.SRAMInitFile(SRAMInitFile) | ||
) u_ibex_demo_system ( | ||
//input | ||
.clk_sys_i(clk_sys), | ||
.rst_sys_ni(rst_sys_n), | ||
.gp_i({SW, BTN}), | ||
.uart_rx_i(UART_RX), | ||
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//output | ||
.gp_o({LED, GPIOS}), | ||
.pwm_o(RGB_LED), | ||
.uart_tx_o(UART_TX), | ||
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.spi_rx_i(SPI_RX), | ||
.spi_tx_o(SPI_TX), | ||
.spi_sck_o(SPI_SCK) | ||
); | ||
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logic IO_RST_N; | ||
assign IO_RST_N = ~IO_RST; | ||
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// Generating the system clock and reset for the FPGA. | ||
clkgen_pynqz2 clkgen( | ||
.IO_CLK, | ||
.IO_RST_N, | ||
.clk_sys, | ||
.rst_sys_n | ||
); | ||
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endmodule |
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# Copyright lowRISC contributors. | ||
# Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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adapter driver ftdi | ||
transport select jtag | ||
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ftdi_device_desc "TUL" | ||
ftdi_vid_pid 0x0403 0x6010 | ||
ftdi_channel 0 | ||
ftdi_layout_init 0x0088 0x008b | ||
reset_config none | ||
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# Configure JTAG chain and the target processor | ||
set _CHIPNAME riscv | ||
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# Configure JTAG expected ID | ||
set _EXPECTED_ID 0x23727093 | ||
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jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version | ||
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# just to avoid a warning about the auto-detected arm core | ||
# see: https://github.com/pulp-platform/riscv-dbg/blob/master/doc/debug-system.md | ||
jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477 | ||
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set _TARGETNAME $_CHIPNAME.cpu | ||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME | ||
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riscv set_ir idcode 0x09 | ||
riscv set_ir dtmcs 0x22 | ||
riscv set_ir dmi 0x23 | ||
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adapter speed 10000 | ||
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riscv set_prefer_sba on | ||
gdb_report_data_abort enable | ||
gdb_report_register_access_error enable | ||
gdb_breakpoint_override hard | ||
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reset_config none | ||
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init | ||
halt |