Configurable UART #57
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…for customizable parameters
…rs and updated the hello world program to demonstrate it
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Thanks again for submitting this PR. We really appreciate you using the Ibex demo system for your thesis and sharing your results with us. I'm not sure if this is possible to merge in in its current state. For example, we usually use .sv files instead of .v files. I've added some initial comments that I went though, but I can totally understand if you have limited bandwidth to do more work on this at this time. Again, thank you for your time and engagement.
sw/c/common/link.ld
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Why are you copying this from sw/common/?
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This is a copy bug, I had a version without the c/rust update and it resulted to this when I copied the folder.
…e,[core] Restored original ibex_demo_system.core the change was a mistake because of the board I used to load the bitstream
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I removed link.ld file and restored the original ibex_demo_system.core file. I understand that the whole project is written in SystemVerilog. Given I have the time and want to be part of this project, I consider rewriting the whole module in SystemVerilog. In general are you interested in the concept of a configurable UART module? Also is there anything else you would like to see included? |
@GregAC can you have a look at this? |
+ Almost full flag for rx/tx sync FIFO + Almost empty flag for rx/tx sync FIFO + Almost full interrupt for tx in C + Almost full / empty flag added to read instruction
[sw] added the volatile qualifier to avoid optimization of empty for block
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I'm sorry for the long delay on responding to this. Although in principle we like the idea of a configurable UART module, I think this PR may require quite a lot of rework and reviewing from our part. This is currently not one of our top priorities. Please do not put too much more effort into this PR as we are unlikely to have a look at this any time soon. Thank you for your interest in the Ibex demo system and we think it is great that you have used and extended it. |
I developed this configurable UART module as part of my thesis, I had opened a previous pull request but when I tried to re-base I had some issues I couldn't solve. Also I finished the document of the thesis, which I will include here.
document