[earlgrey_1.0.0] Update

hw/dv/sv/alert_esc_agent/alert_esc_if.sv

@@ -181,7 +181,7 @@ interface alert_esc_if(input clk, input rst_n);
   endtask : wait_esc_ping
 
   logic alert_sva_active;
-  always_comb alert_sva_active = is_alert && !rst_n;
+  always_comb alert_sva_active = is_alert && rst_n;
 
   // Check the differential alert signals have no unknown values.
   `ASSERT_KNOWN(PingKnown_A, alert_rx.ping_p ^ alert_rx.ping_n, clk, !alert_sva_active)

hw/dv/sv/jtag_agent/jtag_if.sv

@@ -2,8 +2,14 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-// jtag interface with default 50MHz tck
-interface jtag_if #(parameter int unsigned JtagDefaultTckPeriodPs = 20_000) ();
+// TODO(#24580): A JTAG UVM agent should configure the JTAG frequency (and not this interface)
+`ifdef GATE_LEVEL
+  // jtag interface with default 24MHz tck for GLS
+  interface jtag_if #(parameter int unsigned JtagDefaultTckPeriodPs = 20_000) ();
+`else
+  // jtag interface with default 50MHz tck for faster DV simulations
+  interface jtag_if #(parameter int unsigned JtagDefaultTckPeriodPs = 41_664) ();
+`endif
 
   // interface pins
   // TODO; make these wires and add `_oe` versions to internally control the driving of these

hw/ip/pinmux/data/pinmux.hjson

@@ -439,6 +439,7 @@
                             Muxed pad attributes.
                             This register has WARL behavior since not each pad type may support
                             all attributes.
+                            The muxed pad that is used for TAP strap 0 has a different reset value, with `pull_en` set to 1.
                             ''',
                   count:        "NMioPads",
                   compact:      "false",
@@ -509,7 +510,8 @@
                   // read back the same value that was written to them.
                   // further, they have hardware side effects since they drive the
                   // pad attributes, and hence no random data should be written to them.
-                  tags: ["excl:CsrAllTests:CsrExclWrite"]
+                  // Additionally, their reset value is defined by the RTL implementation and may not equal `resval` for all instances (#24621).
+                  tags: ["excl:CsrAllTests:CsrExclAll"]
                 }
     },
 

hw/ip/pinmux/data/pinmux.hjson.tpl

@@ -556,6 +556,7 @@
                             Muxed pad attributes.
                             This register has WARL behavior since not each pad type may support
                             all attributes.
+                            The muxed pad that is used for TAP strap 0 has a different reset value, with `pull_en` set to 1.
                             ''',
                   count:        "NMioPads",
                   compact:      "false",
@@ -626,7 +627,8 @@
                   // read back the same value that was written to them.
                   // further, they have hardware side effects since they drive the
                   // pad attributes, and hence no random data should be written to them.
-                  tags: ["excl:CsrAllTests:CsrExclWrite"]
+                  // Additionally, their reset value is defined by the RTL implementation and may not equal `resval` for all instances (#24621).
+                  tags: ["excl:CsrAllTests:CsrExclAll"]
                 }
     },
 

hw/ip/pinmux/doc/registers.md

@@ -965,6 +965,7 @@ Register write enable for MIO PAD attributes.
 Muxed pad attributes.
 This register has WARL behavior since not each pad type may support
 all attributes.
+The muxed pad that is used for TAP strap 0 has a different reset value, with `pull_en` set to 1.
 - Reset default: `0x0`
 - Reset mask: `0xf300ff`
 

hw/ip/pinmux/lint/pinmux.waiver

@@ -37,3 +37,6 @@ waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'(dio_wkup_mux\[12\]|dio_w
 
 waive -rules CLOCK_MUX -location {pinmux.sv} -regexp {Clock 'dio_in_i\[12\]' reaches a multiplexer here, used as a clock 'clk_i'} \
       -comment "This mux is required to filter designated scan clock inputs (e.g. 'DioSpiDeviceSck' at index 12) from wakeup detector inputs"
+
+waive -rules RESET_ONLY -location {pinmux.sv} -regexp {'mio_pad_attr_q\[0\]' is asynchronously reset but has no other assignments in this block} \
+      -comment "This error can safely be ignored: The signal is obviously driven further down in the very same block, changing the TargetCfg.tap_strap0_idx value to a non-zero value (which it actually is in the Earlgrey top level) makes the error go away."

hw/ip/pinmux/rtl/pinmux.sv

@@ -161,7 +161,17 @@ module pinmux
   always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
     if (!rst_ni) begin
       dio_pad_attr_q <= '0;
-      mio_pad_attr_q <= '0;
+      for (int kk = 0; kk < NMioPads; kk++) begin
+        if (kk == TargetCfg.tap_strap0_idx) begin
+          // TAP strap 0 is sampled after reset (and only once for life cycle states that are not
+          // TEST_UNLOCKED* or RMA).  To ensure it gets sampled as 0 unless driven to 1 from an
+          // external source (and specifically that it gets sampled as 0 when left floating / not
+          // connected), this enables the pull-down of the pad at reset.
+          mio_pad_attr_q[kk] <= '{pull_en: 1'b1, default: '0};
+        end else begin
+          mio_pad_attr_q[kk] <= '0;
+        end
+      end
     end else begin
       // dedicated pads
       for (int kk = 0; kk < NDioPads; kk++) begin

hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson

@@ -552,6 +552,7 @@
                             Muxed pad attributes.
                             This register has WARL behavior since not each pad type may support
                             all attributes.
+                            The muxed pad that is used for TAP strap 0 has a different reset value, with `pull_en` set to 1.
                             ''',
                   count:        "NMioPads",
                   compact:      "false",
@@ -622,7 +623,8 @@
                   // read back the same value that was written to them.
                   // further, they have hardware side effects since they drive the
                   // pad attributes, and hence no random data should be written to them.
-                  tags: ["excl:CsrAllTests:CsrExclWrite"]
+                  // Additionally, their reset value is defined by the RTL implementation and may not equal `resval` for all instances (#24621).
+                  tags: ["excl:CsrAllTests:CsrExclAll"]
                 }
     },