[dv,jtag] Change JTAG clock frequency to 24MHz for GLS - fix the code…

SUMMARY.md

@@ -124,6 +124,7 @@
     - [Programmer's Guide](./hw/ip/ascon/doc/programmers_guide.md)
     - [Hardware Interfaces](./hw/ip/aon_timer/doc/interfaces.md)
     - [Registers](./hw/ip/ascon/doc/registers.md)
+    - [Checklist](./hw/ip/ascon/doc/checklist.md)
   - [Clock Manager](./hw/top_earlgrey/ip_autogen/clkmgr/README.md)
     - [Theory of Operation](./hw/top_earlgrey/ip_autogen/clkmgr/doc/theory_of_operation.md)
     - [Design Verification](./hw/top_earlgrey/ip_autogen/clkmgr/dv/README.md)

hw/dv/sv/jtag_agent/jtag_if.sv

@@ -4,11 +4,11 @@
 
 // TODO(#24580): A JTAG UVM agent should configure the JTAG frequency (and not this interface)
 `ifdef GATE_LEVEL
-  // jtag interface with default 24MHz tck for GLS
-  interface jtag_if #(parameter int unsigned JtagDefaultTckPeriodPs = 20_000) ();
-`else
-  // jtag interface with default 50MHz tck for faster DV simulations
+  // JTAG interface with default 24MHz tck for GLS
   interface jtag_if #(parameter int unsigned JtagDefaultTckPeriodPs = 41_664) ();
+`else
+  // JTAG interface with default 50MHz tck for faster DV simulations
+  interface jtag_if #(parameter int unsigned JtagDefaultTckPeriodPs = 20_000) ();
 `endif
 
   // interface pins

hw/ip/ascon/data/ascon.hjson

@@ -14,9 +14,15 @@
   [graz-ascon]: https://ascon.iaik.tugraz.at/
   [nist-ascon]: https://csrc.nist.gov/Presentations/2023/update-on-standardization-of-ascon-family
   '''
-  regwidth:      "32",
-  cip_id:        "40",
-  version:       "0.0.1",
+  regwidth:           "32",
+  cip_id:             "40",
+  design_spec:        "../doc",
+  hw_checklist:       "../doc/checklist",
+  version:            "0.1.0",
+  life_stage:         "L1",
+  design_stage:       "D0",
+  verification_stage: "V0",
+  dif_stage:          "S0",
   clocking: [
     {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true},
     {clock: "clk_edn_i", reset: "rst_edn_ni", idle: "idle_o"}