coraz7: fix _io

m-labs · Dec 28, 2020 · 60c0f2c · 60c0f2c
1 parent 9a37a58
commit 60c0f2c
Showing 1 changed file with 27 additions and 23 deletions.
diff --git a/migen/build/platforms/coraz7.py b/migen/build/platforms/coraz7.py
@@ -4,7 +4,10 @@
 
 # https://github.com/Digilent/Cora-Z7-10-base-linux/blob/master/src/constraints/Cora-Z7-10-Master.xdc
 _io = [
-    ("sys_clk", 0, Pins("H16"), IOStandard("LVCMOS33")),
+    # FIXME: Though the named IOStandard is specified by the official
+    # constraints file, Vivado demands this pin to be of a pair with
+    # differential signaling.
+    #("clk125", 0, Pins("H16"), IOStandard("LVCMOS33")),
 
     # LED0: B, G, R
     ("user_led", 0, Pins("L15 G17 N15"), IOStandard("LVCMOS33")),
@@ -14,25 +17,26 @@
     ("user_btn", 0, Pins("D20"), IOStandard("LVCMOS33")),
     ("user_btn", 1, Pins("D19"), IOStandard("LVCMOS33")),
 
-    # A
-    ("pmod", 0, Pins("Y18 Y19 Y16 Y17 U18 U19 W18 W19"), IOStandard("LVCMOS33")),
-    # B
-    ("pmod", 1, Pins("W14 Y14 T11 T10 V16 W16 V12 W13"), IOStandard("LVCMOS33")),
-
-    ("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33")),
-
-    ("user_dio", 1, Pins("L19"), IOStandard("LVCMOS33")),
-    ("user_dio", 2, Pins("M19"), IOStandard("LVCMOS33")),
-    ("user_dio", 3, Pins("N20"), IOStandard("LVCMOS33")),
-    ("user_dio", 4, Pins("P20"), IOStandard("LVCMOS33")),
-    ("user_dio", 5, Pins("P19"), IOStandard("LVCMOS33")),
-    ("user_dio", 6, Pins("R19"), IOStandard("LVCMOS33")),
-    ("user_dio", 7, Pins("T20"), IOStandard("LVCMOS33")),
-    ("user_dio", 8, Pins("T19"), IOStandard("LVCMOS33")),
-    ("user_dio", 9, Pins("U20"), IOStandard("LVCMOS33")),
-    ("user_dio", 10, Pins("V20"), IOStandard("LVCMOS33")),
-    ("user_dio", 11, Pins("W20"), IOStandard("LVCMOS33")),
-    ("user_dio", 12, Pins("K19"), IOStandard("LVCMOS33")),
+    ("i2c", 0,
+        Subsignal("sda", Pins("P15")),
+        Subsignal("scl", Pins("P16")),
+        IOStandard("LVCMOS33"),
+    ),
+    ("spi", 0,
+        Subsignal("miso", Pins("W15")),
+        Subsignal("mosi", Pins("T12")),
+        Subsignal("clk", Pins("H15")),
+        Subsignal("cs_n", Pins("F16")),
+        IOStandard("LVCMOS33"),
+    ),
+]
+
+_connectors = [
+    ("pmoda", "Y18 Y19 Y16 Y17 U18 U19 W18 W19"),
+    ("pmodb", "W14 Y14 T11 T10 V16 W16 V12 W13"),
+    ("crypto_sda", "J15"),
+    ("user_dio", "L19 M19 N20 P20 P19 R19 T20 T19 U20 V20 W20 K19"),
+    ("ck_io", "U14 V13 T14 T15 V17 V18 R17 R14 N18 M18 U15 K18 J18 G15 R16 U12 U13 V15 T16 U17 T17 R18 P18 N17 M17 L17 H17 H18 G18 L20"),
 ]
 
 DEVICE_VARIANTS = {
@@ -42,9 +46,9 @@
 
 # Digilent Cora Z7-07S, and Z7-10
 class Platform(XilinxPlatform):
-    default_clk_name = "sys_clk"
-    default_clk_period = 8
+    # default_clk_name = "sys_clk"
+    # default_clk_period = 20
 
     def __init__(self, device_variant="10"):
         device = DEVICE_VARIANTS[device_variant]
-        XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
+        XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")