Update UART Example so that acknowledging RX data sets RX ready low. #344
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
The UART example code currently sets `rx_rdy` high when data has been received. I had assumed that setting `rx_ack` to high would clear this until data is ready again, but in the existing implementation `rx_rdy` only goes low when new data arrives. This small diff changes `rx_ack` to clear `rx_rdy` so that a user can acknowledge data after the first byte and then wait on `rx_rdy` for the next one. I suppose this could've been design with the intent that the user strobes out a signal when `rx_rdy` goes from low to high, but I'm not sure what the use of `rx_ack` is if this was the intended design. Sorry if I'm being oblivious, but if I am, feel free to close out this diff.
louiecaulfield
pushed a commit
to louiecaulfield/nmigen
that referenced
this pull request
Apr 7, 2022
…hdl.verilog.convert and compat.run_simulation Fixes m-labs#344
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
The UART example code currently sets
rx_rdyhigh when data has been received. I had assumed that settingrx_ackto high would clear this until data is ready again, but in the existing implementationrx_rdyonly goes low when new data arrives. This small diff changesrx_ackto clearrx_rdyso that a user can acknowledge data after the first byte and then wait onrx_rdyfor the next one. It also updates the simulation to verify that the right thing happens.I suppose this could've been design with the intent that the user strobes out a signal when
rx_rdygoes from low to high, but I'm not sure what the use ofrx_ackis if this was the intended design. Sorry if I'm being oblivious, but if I am, feel free to close out this diff.