Modified testbench driver

[mmrahorovic]

Previously

1. Input signals would be driven a delta cycle before the falling edge of the clock.
2. List of inputs would be updated (i.e. a check for handshake) would occur a delta cycle before the falling edge, before toggling the clock for a full cycle.

Motivation for change

1. Although functionally correct, it would be better to drive input signals a delta cycle after the rising edge of the clock. Besides making it arguably easier to read the waveform since input signal change at the rising edge, this behavior would be a more realistic simulation of the actual system/network since the input signal is assumed to come from a register from a preceding layer (and hence will only change a delta cycle after the rising edge).
2. The RTL-MVU layer introduced in FINN, opposed to the HLS-based MVU layer, doesn't assert the input tready signal before the tvalid signal is high (they don't depend on each other though, which would be considered a wrong design, but the tready of one input signal depends on whether another input's tvalid is asserted). However, in the first cycle, a valid handshake would occur, despite the prediction based on a delta cycle before the falling edge that it wouldn't. Hence, the same input would be presented twice to the DUT, therefore consumed twice, and thus lead to a wrong output.

Changes introduced

1. Drive input signals a delta cycle after the rising edge.
2. Check for an input/output handshake a delta cycle before the rising edge.

Below is a screenshot of the new waveform.

PR is marked as draft since testing is ongoing.