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Original file line number | Diff line number | Diff line change |
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@@ -1,19 +1,32 @@ | ||
#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] | ||
use core::arch::x86_64::_rdtsc; | ||
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#[derive(Clone, Debug, Default)] | ||
pub struct Counter; | ||
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#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] | ||
impl Counter { | ||
pub fn now(&self) -> u64 { | ||
unsafe { _rdtsc() } | ||
unsafe { ::core::arch::x86_64::_rdtsc() } | ||
} | ||
} | ||
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#[cfg(target_arch = "aarch64")] | ||
impl Counter { | ||
pub fn now(&self) -> u64 { | ||
let count: u64; | ||
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unsafe { | ||
::core::arch::asm!("mrs {}, cntvct_el0", out(reg) count); | ||
} | ||
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count | ||
} | ||
} | ||
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#[cfg(not(all(target_arch = "x86_64", target_feature = "sse2")))] | ||
#[cfg(not(any( | ||
all(target_arch = "x86_64", target_feature = "sse2"), | ||
target_arch = "aarch64", | ||
)))] | ||
impl Counter { | ||
pub fn now(&self) -> u64 { | ||
panic!("can't use counter without TSC support"); | ||
panic!("can't use counter without TSC (x86_64) or system counter (ARM) support"); | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,28 @@ | ||
#[allow(dead_code)] | ||
#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] | ||
pub fn has_counter_support() -> bool { | ||
let cpuid = raw_cpuid::CpuId::new(); | ||
let has_invariant_tsc = cpuid | ||
.get_advanced_power_mgmt_info() | ||
.map_or(false, |apm| apm.has_invariant_tsc()); | ||
let has_rdtscp = cpuid | ||
.get_extended_processor_and_feature_identifiers() | ||
.map_or(false, |epf| epf.has_rdtscp()); | ||
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has_invariant_tsc && has_rdtscp | ||
} | ||
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#[cfg(target_arch = "aarch64")] | ||
pub fn has_counter_support() -> bool { | ||
// AArch64 implies ARMv8 or above, where the system counter is always present. | ||
true | ||
} | ||
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#[allow(dead_code)] | ||
#[cfg(not(any( | ||
all(target_arch = "x86_64", target_feature = "sse2"), | ||
target_arch = "aarch64", | ||
)))] | ||
pub fn has_counter_support() -> bool { | ||
false | ||
} |
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