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Add BITALG and full VPOPCNTDQ instruction support #234

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@vsivsi vsivsi commented Nov 15, 2021

See discussion here: #199 (comment)

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codecov-commenter commented Nov 15, 2021

Codecov Report

Merging #234 (1702e56) into master (ead3fb5) will increase coverage by 0.00%.
The diff coverage is 80.00%.

@@           Coverage Diff           @@
##           master     #234   +/-   ##
=======================================
  Coverage   75.92%   75.92%           
=======================================
  Files          65       65           
  Lines       20694    20719   +25     
=======================================
+ Hits        15711    15731   +20     
- Misses       4901     4906    +5     
  Partials       82       82           
Flag Coverage Δ
integration 11.91% <0.00%> (-0.02%) ⬇️
stress ?
unittests 73.01% <80.00%> (+<0.01%) ⬆️

Flags with carried forward coverage won't be shown. Click here to find out more.

Impacted Files Coverage Δ
x86/zoptab.go 92.42% <ø> (ø)
build/zinstructions.go 67.65% <66.66%> (-0.01%) ⬇️
x86/zctors.go 100.00% <100.00%> (ø)

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mmcloughlin added a commit that referenced this pull request Nov 28, 2022
Supporting extra instructions not included in the Opcodes database is
currently a challenge. Short of migrating to an entirely different source
(such as #23), the options are either to patch the XML data file or to append
additional instructions at the loading phase.

An example of patching the XML was shown in the as-yet unlanded PR #234. This
shows the XML patching approach is unwieldy and requires more information than
we actually need (for example instruction form encodings).

In #335 we discussed the alternative of adding extra instructions during
loading. This has the advantage of using avo's simpler internal data
structure.

This PR prepares for using that approach by adding an `internal/opcodesextra`
package, intended to contain manually curated lists of extra instructions to
add to the instruction database during loading. At the moment, the only
instruction added here is the `MOVLQZX` instruction that's already handled
this way.

Updates #335 #234 #23
@vsivsi vsivsi changed the title Add patch file for BITALG and VL for VPOPCNTDQ Add BITALG and full VPOPCNTDQ instruction support Dec 15, 2022
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vsivsi commented Dec 15, 2022

@mmcloughlin This PR is also now fully merged with upstream and ready to go. I took inspiration from the GFNI PR #344 and backed-out the editing of x86_64.xml I agree, that was a real pain and unsustainable. Using the "opcodesextra" mechanism worked out great.

There was only one wrinkle with this approach, but in the end it seems fine: because x86_64.xml already defines VPOPCNTD and VPOPCNTQ, but without the 128/256 bit "VL" operand forms, the only way to get this to work was to completely redefine and override those two instructions here. There didn't seem to be a clean existing way to "upgrade" the forms already present in x86_64.xml with the VL forms.

mmcloughlin added a commit that referenced this pull request Jan 10, 2023
mmcloughlin added a commit that referenced this pull request Jan 10, 2023
Adds the VPOPCNTDQ instruction set, providing packed population count for
double and quadword integers.

These are added via the `opcodesextra` mechanism #345, since they're missing
from the opcodes database. In this case the 512-bit non-AVX512VL forms are
added here as well as the opcodes database, but they're deduplicated later.

Contributed by @vsivsi. Extracted from #234 with simplifications for AVX-512
form expansion.

Co-authored-by: Vaughn Iverson <[email protected]>
mmcloughlin added a commit that referenced this pull request Jan 11, 2023
mmcloughlin added a commit that referenced this pull request Jan 11, 2023
Adds the AVX-512 Bit Algorithms instruction set.

These new instructions are added via the `opcodesextra` mechanism #345, since
they're missing from the opcodes database.

Contributed by @vsivsi. Extracted from #234 with simplifications for AVX-512
form expansion.

Co-authored-by: Vaughn Iverson <[email protected]>
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Landed in #361 #362.

Thanks!

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3 participants