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[stm32] Remove references to nonexistent 'a0' STM32H7 chip
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WasabiFan committed Sep 19, 2024
1 parent cd4f208 commit beb1ac9
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions src/modm/platform/clock/stm32/module.lb
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ def build(env):
((target["family"] == "f4") and target["name"] in ["46", "69", "79"])

if target.family in ["h7"]:
if target.name in ["a0", "a3", "b0", "b3"]:
if target.name in ["a3", "b0", "b3"]:
properties["cfgr_prescaler"] = "CDCFGR1"
else:
properties["cfgr_prescaler"] = "D1CFGR"
Expand All @@ -96,7 +96,7 @@ def build(env):
properties["cfgr_prescaler"] = "CFGR"

if target.family in ["h7"]:
if target.name in ["a0", "a3", "b0", "b3"]:
if target.name in ["a3", "b0", "b3"]:
properties["cfgr2"] = "CDCFGR2"
else:
properties["cfgr2"] = "D2CFGR"
Expand All @@ -115,9 +115,9 @@ def build(env):
else:
properties["ccipr1"] = "CCIPR"

properties["d1"] = ("CD" if target.name in ["a0", "a3", "b0", "b3"] else "D1") \
properties["d1"] = ("CD" if target.name in ["a3", "b0", "b3"] else "D1") \
if target.family == "h7" else ""
properties["d2"] = ("CD" if target.name in ["a0", "a3", "b0", "b3"] else "D2") \
properties["d2"] = ("CD" if target.name in ["a3", "b0", "b3"] else "D2") \
if target.family == "h7" else ""
properties["cfgr3"] = ("SRDCFGR" if target.name in ["a0", "a3", "b0", "b3"] else "D3CFGR")
properties["d3"] = ("SRD" if target.name in ["a0", "a3", "b0", "b3"] else "D3")
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