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Still troubles with flashing onto target
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FranzForstmayr committed Aug 21, 2024
1 parent ea586ef commit ed038e1
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Showing 3 changed files with 47 additions and 1 deletion.
2 changes: 2 additions & 0 deletions src/modm/board/disco_u083c/board.xml
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Expand Up @@ -7,6 +7,8 @@

<options>
<option name="modm:target">stm32u083mct6</option>
<option name="modm:platform:cortex-m:main_stack_size">1Ki</option>
<option name="modm:build:openocd.cfg">openocd.cfg</option>
</options>
<modules>
<module>modm:board:disco-u083c</module>
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2 changes: 1 addition & 1 deletion src/modm/board/disco_u083c/module.lb
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Expand Up @@ -37,4 +37,4 @@ def build(env):
}
env.template("../board.cpp.in", "board.cpp")
env.copy('.')
env.collect(":build:openocd.source", "board/STM32U083C-DK.cfg")
env.collect(":build:openocd.source")
44 changes: 44 additions & 0 deletions src/modm/board/disco_u083c/openocd.cfg
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# This is an STM32U083C-DK board with a single STM32U083MCTx chip
#
# Generated by STM32CubeIDE
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)

source [find interface/stlink-dap.cfg]


set WORKAREASIZE 0x8000

transport select "dapdirect_swd"

set CHIPNAME STM32U083MCTx
set BOARDNAME STM32U083C-DK

# Enable debug when in low power modes
set ENABLE_LOW_POWER 1

# Stop Watchdog counters when halt
set STOP_WATCHDOG 1

# STlink Debug clock frequency
set CLOCK_FREQ 8000

# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0

# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 3333





# BCTM CPU variables

source [find target/stm32u0x.cfg]

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