A multi-chip multi-chiplet Simulator for data-centric execution. Particularly suited for simulating large compositions of manycore chips with a partitioned global address space (PGAS).
This simulator is written entirely in C/C++. It has been tested with G++ version 12 and 13.
It requires OpenMP.
The scripts inside the plots folder require Python version 3. These scripts parse the simulator traces generated by the experiments to create plots.
Because many parameters are passed as macros, the simulator is compiled every time that a new experiment is launched. There are scripts that launch experiments. Those are stored in the exp/ folder. For example one can use the following command to run Sparse Matrix Vector Multiplication (SPMV), which corresponds to application #4 from the 7 applications that are included in this simulator by default.
exp/run_app.sh 4 0 A
The '0' refers to the configuration set inside the run_app.sh script.
The 'A' refers to the name we are giving to the experiment. This 'A' is also considered the name for the binary created inside the bin folder.
The simulator has many configuration parameters inside src/configs. Other parameters are set as C macros inside exp/run.sh which is the file where the simulator gets compiled. The reason why some parameters are macros is for simulation efficiency, so that the code inside the ifdef macros is only executed if that parameter is set.
src containss the source files of the simulator
doall contain the sequential or doall implementations of some of the applications included as benchmarks inside this simulator.
sim_logs is the folder where simulation traces are generated into.
bin contains the binary files created by the compilation of different experiments.
datasets contains the datasets in binary format and TSV format.
exp contains experiments scrips.
gui contains a PyQt5 GUI to show plots based on simulation traces. (Installation instructions contained inside that folder.)
plots contains python scripts to plot heatmaps and other characterization plots for different experiments.
More information about muchiSim concepts are found on src/README.md
MuchiSim has helped evaluating "Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees ", and "DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications".