clk: qcom: skip setting rate if not needed for pixel, byte2 ops

Skip setting rate for clk_pixel_ops and clk_byte2+ops when clock is
already enabled on same rate, so following warning won't be produced.

 byte0_clk_src: rcg didn't update its configuration.
 WARNING: CPU: 0 PID: 12 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc4/0xd8
 Modules linked in:
 CPU: 0 PID: 12 Comm: kworker/0:1 Not tainted 5.6.0-rc3-postmarketos-qcom-msm8953-00022-ga0e3878d15f8-dirty #190
 Hardware name: Samsung A6-Plus LTE Rev.4 (DT)
 Workqueue: events deferred_probe_work_func
 pstate: 60000005 (nZCv daif -PAN -UAO)
 pc : update_config+0xc4/0xd8
 lr : update_config+0xc4/0xd8
 sp : ffff800011cbb0f0
 x29: ffff800011cbb0f0 x28: ffff0000acb6ccc0
 x27: ffff800010879b18 x26: ffff0000adc9e9a8
 x25: 0000000000000000 x24: 000000000773286c
 x23: ffff800010bfb848 x22: ffff800010a27178
 x21: ffff0000add09b00 x20: ffff800010bfb848
 x19: 0000000000000000 x18: 0000000000000020
 x17: 0000000000011940 x16: 0000000000000006
 x15: ffff0000add09f50 x14: ffffffffffffffff
 x13: 0000000000000000 x12: ffff800010c76000
 x11: ffff800010bad000 x10: ffff800010c764c8
 x9 : ffff80001010cb48 x8 : 6974617275676966
 x7 : 6e6f632073746920 x6 : ffff800010c76533
 x5 : 0000000000000000 x4 : 0000000000000000
 x3 : 00000000ffffffff x2 : ffff8000a0da4000
 x1 : 78c520ed39868900 x0 : 0000000000000000
 Call trace:
  update_config+0xc4/0xd8
  clk_rcg2_configure+0x28/0x38
  clk_byte2_set_rate+0xdc/0x110
  clk_change_rate+0x100/0x540
  clk_core_set_rate_nolock+0x1ac/0x200
  clk_set_rate+0x3c/0xa8
  dsi_link_clk_set_rate_6g+0x40/0xe8
  msm_dsi_host_power_on+0x130/0x6a0
  dsi_mgr_bridge_pre_enable+0x1f4/0x318
  drm_atomic_bridge_chain_pre_enable+0x80/0x98
  drm_atomic_helper_commit_modeset_enables+0x11c/0x250
  msm_atomic_commit_tail+0x178/0x838
  commit_tail+0xa4/0x188
  drm_atomic_helper_commit+0x148/0x178
  drm_atomic_commit+0x50/0x60
  drm_client_modeset_commit_atomic.isra.0+0x17c/0x230
  drm_client_modeset_commit_force+0x60/0x198
  drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xd8
  drm_fb_helper_set_par+0x34/0x68
  fbcon_init+0x3cc/0x590
  visual_init+0xb4/0x108
  do_bind_con_driver+0x1d4/0x3a8
  do_take_over_console+0x144/0x200
  do_fbcon_takeover+0x70/0xd8
  fbcon_fb_registered+0x100/0x110
  register_framebuffer+0x208/0x318
  __drm_fb_helper_initial_config_and_unlock+0x300/0x4a8
  drm_fb_helper_initial_config+0x4c/0x58
  msm_fbdev_init+0x90/0xf0
  msm_drm_bind+0x5d8/0x650
  try_to_bring_up_master+0x268/0x2f0
  __component_add+0xd0/0x198
  component_add+0x18/0x20
  dsi_dev_probe+0x20/0x28
  platform_drv_probe+0x58/0xa8
  really_probe+0x120/0x438
  driver_probe_device+0x9c/0x138
  __device_attach_driver+0xb0/0x120
  bus_for_each_drv+0x7c/0xc8
  __device_attach+0xe4/0x168
  device_initial_probe+0x18/0x20
  bus_probe_device+0x98/0xa0
  deferred_probe_work_func+0xa4/0xe0
  process_one_work+0x1c0/0x468
  worker_thread+0x50/0x428
  kthread+0x104/0x130
  ret_from_fork+0x10/0x18
 ---[ end trace 212da46ab98f1674 ]---

drivers/clk/qcom/clk-rcg2.c

@@ -597,6 +597,10 @@ static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate,
 	u32 mask = BIT(rcg->hid_width) - 1;
 	u32 cfg;
 
+	if (clk_rcg2_is_enabled(hw) &&
+	    rate == clk_rcg2_recalc_rate(hw, parent_rate))
+		return 0;
+
 	div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
 	div = min_t(u32, div, mask);
 
@@ -677,6 +681,11 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 	u32 hid_div, cfg;
 	int i, num_parents = clk_hw_get_num_parents(hw);
 
+
+	if (clk_rcg2_is_enabled(hw) &&
+	    rate == clk_rcg2_recalc_rate(hw, parent_rate))
+		return 0;
+
 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
 	cfg &= CFG_SRC_SEL_MASK;
 	cfg >>= CFG_SRC_SEL_SHIFT;