LimeSDR Gateware

This project focuses on the development and customization of FPGA gateware for LimeSDR boards using the LiteX framework.

Available branches

More details can be found in:

Name		Name	Last commit message	Last commit date
Latest commit History 135 Commits
docs		docs
firmware		firmware
gateware		gateware
software		software
.gitignore		.gitignore
.gitmodules		.gitmodules
README.rst		README.rst
cntrl.csv		cntrl.csv
cntrl_analyzer.csv		cntrl_analyzer.csv
digilent_hs2.cfg		digilent_hs2.cfg
fairwaves_xtrx_platform.py		fairwaves_xtrx_platform.py
lime_top_analyzer.csv		lime_top_analyzer.csv
lime_top_rx_path_analyzer.csv		lime_top_rx_path_analyzer.csv
limesdr_xtrx.cfg		limesdr_xtrx.cfg
limesdr_xtrx.py		limesdr_xtrx.py
limesdr_xtrx_platform.py		limesdr_xtrx_platform.py
openocd_xc7_ft2232.cfg		openocd_xc7_ft2232.cfg
riscv_jtag_tunneled.tcl		riscv_jtag_tunneled.tcl
stream.cfg		stream.cfg