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Merge branch 'master' into assert-eq-builtin
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* master:
  feat(ssa): Merge slices in if statements with witness conditions (#2347)
  chore: Separate frontend `Visibility` and `Distinctness` from the ABI (#2369)
  feat: add syntax for specifying function type environments (#2357)
  chore: Remove unused `Directive::Log` (#2366)
  chore: clippy fixes (#2365)
  chore: Extract bytecode from artifact files for backend integration test inputs (#2356)
  feat: Add trait definition representation in DefCollector and HIR (#2338)
  chore: Remove unused `Intrinsic::Println` (#2358)
  fix: Remove duplicte `T` in `expected T, found T` error on tuple assignment (#2360)
  chore(brillig): Fix brillig radix instruction return vector size (#2350)
  fix: Show types in error message in same order as in source code (#2353)
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TomAFrench committed Aug 19, 2023
2 parents 11a410b + 76f7e43 commit 49f0d95
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Showing 318 changed files with 1,321 additions and 521 deletions.
2 changes: 1 addition & 1 deletion crates/lsp/src/lib.rs
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Expand Up @@ -520,7 +520,7 @@ fn on_did_save_text_document(
}

// We need to refresh lenses when we compile since that's the only time they can be accurately reflected
let _ = state.client.code_lens_refresh(());
std::mem::drop(state.client.code_lens_refresh(()));

let _ = state.client.publish_diagnostics(PublishDiagnosticsParams {
uri: params.text_document.uri,
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22 changes: 17 additions & 5 deletions crates/nargo/src/ops/foreign_calls.rs
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@@ -1,5 +1,5 @@
use acvm::{
acir::brillig::{ForeignCallResult, Value},
acir::brillig::{ForeignCallOutput, ForeignCallResult, Value},
pwg::ForeignCallWaitInfo,
};
use iter_extended::vecmap;
Expand Down Expand Up @@ -54,13 +54,25 @@ impl ForeignCall {
}
Some(ForeignCall::Sequence) => {
let sequence_length: u128 = foreign_call.inputs[0][0].to_field().to_u128();

Ok(vecmap(0..sequence_length, Value::from).into())
let sequence = vecmap(0..sequence_length, Value::from);

Ok(ForeignCallResult {
values: vec![
ForeignCallOutput::Single(sequence_length.into()),
ForeignCallOutput::Array(sequence),
],
})
}
Some(ForeignCall::ReverseSequence) => {
let sequence_length: u128 = foreign_call.inputs[0][0].to_field().to_u128();

Ok(vecmap((0..sequence_length).rev(), Value::from).into())
let sequence = vecmap((0..sequence_length).rev(), Value::from);

Ok(ForeignCallResult {
values: vec![
ForeignCallOutput::Single(sequence_length.into()),
ForeignCallOutput::Array(sequence),
],
})
}
None => panic!("unexpected foreign call {:?}", foreign_call_name),
}
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@@ -0,0 +1,7 @@
[package]
name = "slice_access_failure"
type = "bin"
authors = [""]
compiler_version = "0.10.2"

[dependencies]
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@@ -0,0 +1,2 @@
x = "5"
y = "10"
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@@ -0,0 +1,13 @@
fn main(x : Field, y : pub Field) {
let mut slice = [0; 2];
if x == y {
slice = slice.push_back(y);
slice = slice.push_back(x);
} else {
slice = slice.push_back(x);
}
// This constraint should fail as the slice length is 3 and the index is 3
// The right hand side AND case ensures that the circuit inputs have not changed
// and we always hit the else case in the if statement above.
assert((slice[3] == 0) & (slice[2] != y));
}
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1 change: 0 additions & 1 deletion crates/nargo_cli/tests/execution_success/6/target/6.json

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