python3-grpcio: Fix build with riscv32

Ensure libseil-cpp can build for rv32 and boringssl riscv patch
considers rv32 separate from rv64

Signed-off-by: Khem Raj <[email protected]>

meta-python/recipes-devtools/python/python3-grpcio/0001-Fix-build-on-riscv32.patch

@@ -0,0 +1,65 @@
+From 04e28fdda03b545a0f7b446a784ec2fa7249cbb8 Mon Sep 17 00:00:00 2001
+From: Khem Raj <[email protected]>
+Date: Wed, 29 Apr 2020 15:37:40 -0700
+Subject: [PATCH] Fix build on riscv32
+
+Define __NR_mmap in terms of __NR_mmap2 and __NR_futex interms of
+__NR_futex_time64 for rv32, since there calls dont exist for rv32
+
+Also recognise rv32 as a new 32bit platform
+
+Upstream-Status: Submitted [https://github.com/abseil/abseil-cpp/pull/675]
+Signed-off-by: Khem Raj <[email protected]>
+---
+ absl/base/internal/direct_mmap.h        | 5 +++++
+ absl/base/internal/spinlock_linux.inc   | 4 ++++
+ absl/synchronization/internal/waiter.cc | 4 ++++
+ 3 files changed, 13 insertions(+)
+
+--- a/third_party/abseil-cpp/absl/base/internal/direct_mmap.h
++++ b/third_party/abseil-cpp/absl/base/internal/direct_mmap.h
+@@ -26,6 +26,10 @@
+
+ #ifdef __linux__
+
++#if !defined(__NR_mmap) && defined(__riscv) && __riscv_xlen == 32
++# define __NR_mmap __NR_mmap2
++#endif
++
+ #include <sys/types.h>
+ #ifdef __BIONIC__
+ #include <sys/syscall.h>
+@@ -72,6 +76,7 @@ inline void* DirectMmap(void* start, siz
+ #if defined(__i386__) || defined(__ARM_ARCH_3__) || defined(__ARM_EABI__) || \
+     (defined(__mips__) && _MIPS_SIM == _MIPS_SIM_ABI32) ||                   \
+     (defined(__PPC__) && !defined(__PPC64__)) ||                             \
++    (defined(__riscv) && __riscv_xlen == 32)  ||                             \
+     (defined(__s390__) && !defined(__s390x__))
+   // On these architectures, implement mmap with mmap2.
+   static int pagesize = 0;
+--- a/third_party/abseil-cpp/absl/base/internal/spinlock_linux.inc
++++ b/third_party/abseil-cpp/absl/base/internal/spinlock_linux.inc
+@@ -14,6 +14,10 @@
+ //
+ // This file is a Linux-specific part of spinlock_wait.cc
+
++#if !defined(__NR_futex) && defined(__riscv) && __riscv_xlen == 32
++# define __NR_futex __NR_futex_time64
++#endif
++
+ #include <linux/futex.h>
+ #include <sys/syscall.h>
+ #include <unistd.h>
+--- a/third_party/abseil-cpp/absl/synchronization/internal/waiter.cc
++++ b/third_party/abseil-cpp/absl/synchronization/internal/waiter.cc
+@@ -24,6 +24,10 @@
+ #include <unistd.h>
+ #endif
+
++#if !defined(__NR_futex) && defined(__riscv) && __riscv_xlen == 32
++# define __NR_futex __NR_futex_time64
++#endif
++
+ #ifdef __linux__
+ #include <linux/futex.h>
+ #include <sys/syscall.h>

meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch

@@ -4,13 +4,18 @@ Upstream-Status: Pending
 Signed-off-by: Khem Raj <[email protected]>
 --- a/third_party/boringssl/include/openssl/base.h
 +++ b/third_party/boringssl/include/openssl/base.h
-@@ -108,6 +108,9 @@ extern "C" {
+@@ -108,6 +108,14 @@ extern "C" {
  #elif defined(__mips__) && defined(__LP64__)
  #define OPENSSL_64_BIT
  #define OPENSSL_MIPS64
-+#elif defined(__riscv) && defined(__riscv_xlen)
-+#define OPENSSL_64_BIT
-+#define OPENSSL_RISCV64
++#elif defined(__riscv)
++# if (__riscv_xlen == 64)
++#  define OPENSSL_64_BIT
++#  define OPENSSL_RISCV64
++# elif(__riscv_xlen == 32)
++#  define OPENSSL_32_BIT
++#  define OPENSSL_RISCV32
++# endif
  #elif defined(__pnacl__)
  #define OPENSSL_32_BIT
  #define OPENSSL_PNACL

meta-python/recipes-devtools/python/python3-grpcio_1.27.1.bb

@@ -9,6 +9,7 @@ DEPENDS += "${PYTHON_PN}-protobuf"
 SRC_URI += "file://0001-setup.py-Do-not-mix-C-and-C-compiler-options.patch"
 SRC_URI_append_class-target = " file://ppc-boringssl-support.patch \
                                 file://riscv64_support.patch \
+                                file://0001-Fix-build-on-riscv32.patch \
 "
 SRC_URI[md5sum] = "ccaf4e7eb4f031d926fb80035d193b98"
 SRC_URI[sha256sum] = "a899725d34769a498ecd3be154021c4368dd22bdc69473f6ec46779696f626c4"