Add support for Post-Incrementing Load & Store Instructions.
Add support for Register-Register Load & Store Instructions.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Support at most 2 nested hardware loop with following constraints:

- Start and End addresses of an HWLoop must be 32-bit aligned.
- End Address must be strictly greater than Start Address.
- End address of an HWLoop must point to the instruction just after the
  last one of the HWLoop body.
- HWLoop body must contain at least 3 instructions.
- When both loops are nested, the End address of the outermost HWLoop
  (must be #1) must be at least 2 instructions further than the End address
  of the innermost HWLoop (must be #0), i.e. HWLoop[1].endaddress >=
  HWLoop[0].endaddress + 8.
- HWLoop must always be entered from its start location (no branch/jump
  to a location inside a HWLoop body).
- No HWLoop #0 (resp. #1) CSR should be modified inside the HWLoop #0
  (resp. #1) body.
- No Compressed instructions (RVC) allowed in the HWLoop body.
- No jump or branch instructions allowed in the HWLoop body.
- No memory ordering instructions (fence, fence.i) allowed in the HWLoop body.
- No privileged instructions (mret, dret, ecall, wfi) allowed in the HWLoop
  body, except for ebreak.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp SIMD add/sub/avg{u}/min{u}/max{u} instructions.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp SIMD shift instructions.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp SIMD or/and/xor/abs/extract{u}/insert instructions.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp SIMD {s}dot{up/sp/usp} instructions.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp SIMD shuffle and pack related instructions.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp SIMD cmp{eq/ne/gt{u}/ge{u}/lt{u}/le{u}} instructions.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp SIMD subrotmj/cplxconf/cplxmul/add.div*/sub.div*
instructions.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp Multiply-Accumulate instructions such as cv_mac/
msu/muluN...

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Xpulp Bit Manipulation instructions such as
cv_extract{u}/insert/bclr...

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for General ALU instructions such as cv_abs/slet/clip/addN...

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Add support for Immediate Branching instructions cv_beqimm/bneimm.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

Expose xcv* properties and set the default value to false.

Signed-off-by: Weiwei Li <[email protected]>
Signed-off-by: Junqiang Wang <[email protected]>

… rs1)

for post-incremented loads (rs1!), loaded data has highest priority over
incremented address when writing to this same register.