RISC-V ISA Formal Verification setup and script files for Siemens Questa Processor tool #314
Workflow file for this run
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| name: check_target | |
| on: [push, pull_request] | |
| jobs: | |
| check_target: | |
| runs-on: ubuntu-latest | |
| steps: | |
| - if: ${{ (github.event.pull_request.head.ref == 'dev' && github.event.pull_request.base.ref == 'master') || github.event.pull_request.base.ref == 'dev' || github.event.push.ref != 'refs/heads/master'}} | |
| run: exit 0 | |
| - if: ${{ github.event.pull_request.base.ref != 'dev' || github.event.push.ref == 'refs/heads/master'}} | |
| run: exit 1 |