Merge pull request #881 from pascalgouedo/dev_dd_pgo_rtl

5 RTL issues corrections + 1 former correction improvement
openhwgroup · Oct 4, 2023 · 7df7d2d · 7df7d2d
2 parents 8a6f74b + 767fb0f
commit 7df7d2d
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Showing 4 changed files with 28 additions and 7 deletions.
diff --git a/rtl/cv32e40p_controller.sv b/rtl/cv32e40p_controller.sv
@@ -226,6 +226,8 @@ module cv32e40p_controller import cv32e40p_pkg::*;
   logic hwlp_counter1_gt_1;
   logic hwlp_counter0_eq_1;
   logic hwlp_counter1_eq_1;
+  logic hwlp_counter0_eq_0;
+  logic hwlp_counter1_eq_0;
   logic hwlp_end0_eq_pc_plus4;
   logic hwlp_end1_eq_pc_plus4;
   logic hwlp_start0_leq_pc;
@@ -816,8 +818,8 @@ module cv32e40p_controller import cv32e40p_pkg::*;
                             ctrl_fsm_ns      = is_hwlp_body ? DECODE_HWLOOP : DECODE;
                       end
 
-                      hwlp_dec_cnt_o[0] = hwlp_end0_eq_pc;
-                      hwlp_dec_cnt_o[1] = hwlp_end1_eq_pc;
+                      hwlp_dec_cnt_o[0] = hwlp_end0_eq_pc && !hwlp_counter0_eq_0;
+                      hwlp_dec_cnt_o[1] = hwlp_end1_eq_pc && !hwlp_counter1_eq_0;
 
                     end
                   endcase // unique case (1'b1)
@@ -1275,6 +1277,8 @@ generate
     assign hwlp_counter1_gt_1      = hwlp_counter_i[1] > 1;
     assign hwlp_counter0_eq_1      = hwlp_counter_i[0] == 1;
     assign hwlp_counter1_eq_1      = hwlp_counter_i[1] == 1;
+    assign hwlp_counter0_eq_0      = hwlp_counter_i[0] == 0;
+    assign hwlp_counter1_eq_0      = hwlp_counter_i[1] == 0;
     assign hwlp_end0_eq_pc_plus4   = hwlp_end_addr_i[0] == pc_id_i + 8;   // Equivalent to hwlp_end_addr_i[0] - 4 == pc_id_i + 4
     assign hwlp_end1_eq_pc_plus4   = hwlp_end_addr_i[1] == pc_id_i + 8;   // Equivalent to hwlp_end_addr_i[1] - 4 == pc_id_i + 4
     assign hwlp_start0_leq_pc      = hwlp_start_addr_i[0] <= pc_id_i;
@@ -1293,6 +1297,8 @@ generate
     assign hwlp_counter1_gt_1      = 1'b0;
     assign hwlp_counter0_eq_1      = 1'b0;
     assign hwlp_counter1_eq_1      = 1'b0;
+    assign hwlp_counter0_eq_0      = 1'b0;
+    assign hwlp_counter1_eq_0      = 1'b0;
     assign hwlp_end0_eq_pc_plus4   = 1'b0;
     assign hwlp_end1_eq_pc_plus4   = 1'b0;
     assign hwlp_start0_leq_pc      = 1'b0;

diff --git a/rtl/cv32e40p_core.sv b/rtl/cv32e40p_core.sv
@@ -780,6 +780,8 @@ module cv32e40p_core
 
       .mult_multicycle_o(mult_multicycle),  // to ID/EX pipe registers
 
+      .data_req_i          (data_req_o),  // from ID/EX pipeline
+      .data_rvalid_i       (data_rvalid_i),  // from ID/EX pipeline
       .data_misaligned_ex_i(data_misaligned_ex),  // from ID/EX pipeline
       .data_misaligned_i   (data_misaligned),
 

diff --git a/rtl/cv32e40p_ex_stage.sv b/rtl/cv32e40p_ex_stage.sv
@@ -76,6 +76,8 @@ module cv32e40p_ex_stage
 
     output logic mult_multicycle_o,
 
+    input logic data_req_i,
+    input logic data_rvalid_i,
     input logic data_misaligned_ex_i,
     input logic data_misaligned_i,
 
@@ -369,19 +371,19 @@ module cv32e40p_ex_stage
           apu_result_q <= 'b0;
           apu_flags_q  <= 'b0;
         end else begin
-          if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) begin
+          if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || (data_req_i && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
             apu_rvalid_q <= 1'b1;
             apu_result_q <= apu_result_i;
             apu_flags_q  <= apu_flags_i;
-          end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) begin
+          end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
             apu_rvalid_q <= 1'b0;
           end
         end
       end
 
       assign apu_req_o = apu_req;
       assign apu_gnt = apu_gnt_i;
-      assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
+      assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
       assign apu_operands_o = apu_operands_i;
       assign apu_op_o = apu_op_i;
       assign apu_result = apu_rvalid_q ? apu_result_q : apu_result_i;

diff --git a/rtl/cv32e40p_id_stage.sv b/rtl/cv32e40p_id_stage.sv
@@ -832,14 +832,23 @@ module cv32e40p_id_stage
             apu_read_regs[1]       = regfile_addr_ra_id;
             apu_read_regs_valid[1] = 1'b1;
           end
-          OP_B_REGB_OR_FWD: begin
+          OP_B_REGB_OR_FWD, OP_B_BMASK: begin
             apu_read_regs[1]       = regfile_addr_rb_id;
             apu_read_regs_valid[1] = 1'b1;
           end
           OP_B_REGC_OR_FWD: begin
             apu_read_regs[1]       = regfile_addr_rc_id;
             apu_read_regs_valid[1] = 1'b1;
           end
+          OP_B_IMM: begin
+            if (alu_bmask_b_mux_sel == BMASK_B_REG) begin
+              apu_read_regs[1]       = regfile_addr_rb_id;
+              apu_read_regs_valid[1] = 1'b1;
+            end else begin
+              apu_read_regs[1]       = regfile_addr_rb_id;
+              apu_read_regs_valid[1] = 1'b0;
+            end
+          end
           default: begin
             apu_read_regs[1]       = regfile_addr_rb_id;
             apu_read_regs_valid[1] = 1'b0;
@@ -854,7 +863,9 @@ module cv32e40p_id_stage
             apu_read_regs_valid[2] = 1'b1;
           end
           OP_C_REGC_OR_FWD: begin
-            if ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR)) begin
+            if ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR) &&
+                !((alu_op_b_mux_sel == OP_B_IMM) && (alu_bmask_b_mux_sel == BMASK_B_REG)) &&
+                !(alu_op_b_mux_sel == OP_B_BMASK)) begin
               apu_read_regs[2]       = regfile_addr_rc_id;
               apu_read_regs_valid[2] = 1'b1;
             end else begin