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5 RTL issues corrections + 1 former correction improvement #881

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Oct 4, 2023
Merged

5 RTL issues corrections + 1 former correction improvement #881

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c493675
Narrower correction of issues #731/#742
Oct 2, 2023
eb0668c
Issues #869/#870/#876/#877 correction.
Oct 2, 2023
767fb0f
Issue #880 correction.
Oct 2, 2023
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10 changes: 8 additions & 2 deletions rtl/cv32e40p_controller.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -226,6 +226,8 @@ module cv32e40p_controller import cv32e40p_pkg::*;
logic hwlp_counter1_gt_1;
logic hwlp_counter0_eq_1;
logic hwlp_counter1_eq_1;
logic hwlp_counter0_eq_0;
logic hwlp_counter1_eq_0;
logic hwlp_end0_eq_pc_plus4;
logic hwlp_end1_eq_pc_plus4;
logic hwlp_start0_leq_pc;
Expand Down Expand Up @@ -816,8 +818,8 @@ module cv32e40p_controller import cv32e40p_pkg::*;
ctrl_fsm_ns = is_hwlp_body ? DECODE_HWLOOP : DECODE;
end

hwlp_dec_cnt_o[0] = hwlp_end0_eq_pc;
hwlp_dec_cnt_o[1] = hwlp_end1_eq_pc;
hwlp_dec_cnt_o[0] = hwlp_end0_eq_pc && !hwlp_counter0_eq_0;
hwlp_dec_cnt_o[1] = hwlp_end1_eq_pc && !hwlp_counter1_eq_0;

end
endcase // unique case (1'b1)
Expand Down Expand Up @@ -1275,6 +1277,8 @@ generate
assign hwlp_counter1_gt_1 = hwlp_counter_i[1] > 1;
assign hwlp_counter0_eq_1 = hwlp_counter_i[0] == 1;
assign hwlp_counter1_eq_1 = hwlp_counter_i[1] == 1;
assign hwlp_counter0_eq_0 = hwlp_counter_i[0] == 0;
assign hwlp_counter1_eq_0 = hwlp_counter_i[1] == 0;
assign hwlp_end0_eq_pc_plus4 = hwlp_end_addr_i[0] == pc_id_i + 8; // Equivalent to hwlp_end_addr_i[0] - 4 == pc_id_i + 4
assign hwlp_end1_eq_pc_plus4 = hwlp_end_addr_i[1] == pc_id_i + 8; // Equivalent to hwlp_end_addr_i[1] - 4 == pc_id_i + 4
assign hwlp_start0_leq_pc = hwlp_start_addr_i[0] <= pc_id_i;
Expand All @@ -1293,6 +1297,8 @@ generate
assign hwlp_counter1_gt_1 = 1'b0;
assign hwlp_counter0_eq_1 = 1'b0;
assign hwlp_counter1_eq_1 = 1'b0;
assign hwlp_counter0_eq_0 = 1'b0;
assign hwlp_counter1_eq_0 = 1'b0;
assign hwlp_end0_eq_pc_plus4 = 1'b0;
assign hwlp_end1_eq_pc_plus4 = 1'b0;
assign hwlp_start0_leq_pc = 1'b0;
Expand Down
2 changes: 2 additions & 0 deletions rtl/cv32e40p_core.sv
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Expand Up @@ -780,6 +780,8 @@ module cv32e40p_core

.mult_multicycle_o(mult_multicycle), // to ID/EX pipe registers

.data_req_i (data_req_o), // from ID/EX pipeline
.data_rvalid_i (data_rvalid_i), // from ID/EX pipeline
.data_misaligned_ex_i(data_misaligned_ex), // from ID/EX pipeline
.data_misaligned_i (data_misaligned),

Expand Down
8 changes: 5 additions & 3 deletions rtl/cv32e40p_ex_stage.sv
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Expand Up @@ -76,6 +76,8 @@ module cv32e40p_ex_stage

output logic mult_multicycle_o,

input logic data_req_i,
input logic data_rvalid_i,
input logic data_misaligned_ex_i,
input logic data_misaligned_i,

Expand Down Expand Up @@ -369,19 +371,19 @@ module cv32e40p_ex_stage
apu_result_q <= 'b0;
apu_flags_q <= 'b0;
end else begin
if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) begin
if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || (data_req_i && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
apu_rvalid_q <= 1'b1;
apu_result_q <= apu_result_i;
apu_flags_q <= apu_flags_i;
end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) begin
end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
apu_rvalid_q <= 1'b0;
end
end
end

assign apu_req_o = apu_req;
assign apu_gnt = apu_gnt_i;
assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
assign apu_operands_o = apu_operands_i;
assign apu_op_o = apu_op_i;
assign apu_result = apu_rvalid_q ? apu_result_q : apu_result_i;
Expand Down
15 changes: 13 additions & 2 deletions rtl/cv32e40p_id_stage.sv
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Expand Up @@ -832,14 +832,23 @@ module cv32e40p_id_stage
apu_read_regs[1] = regfile_addr_ra_id;
apu_read_regs_valid[1] = 1'b1;
end
OP_B_REGB_OR_FWD: begin
OP_B_REGB_OR_FWD, OP_B_BMASK: begin
apu_read_regs[1] = regfile_addr_rb_id;
apu_read_regs_valid[1] = 1'b1;
end
OP_B_REGC_OR_FWD: begin
apu_read_regs[1] = regfile_addr_rc_id;
apu_read_regs_valid[1] = 1'b1;
end
OP_B_IMM: begin
if (alu_bmask_b_mux_sel == BMASK_B_REG) begin
apu_read_regs[1] = regfile_addr_rb_id;
apu_read_regs_valid[1] = 1'b1;
end else begin
apu_read_regs[1] = regfile_addr_rb_id;
apu_read_regs_valid[1] = 1'b0;
end
end
default: begin
apu_read_regs[1] = regfile_addr_rb_id;
apu_read_regs_valid[1] = 1'b0;
Expand All @@ -854,7 +863,9 @@ module cv32e40p_id_stage
apu_read_regs_valid[2] = 1'b1;
end
OP_C_REGC_OR_FWD: begin
if ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR)) begin
if ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR) &&
!((alu_op_b_mux_sel == OP_B_IMM) && (alu_bmask_b_mux_sel == BMASK_B_REG)) &&
!(alu_op_b_mux_sel == OP_B_BMASK)) begin
apu_read_regs[2] = regfile_addr_rc_id;
apu_read_regs_valid[2] = 1'b1;
end else begin
Expand Down
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