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Ariane 4.2
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@msfschaffner msfschaffner released this 04 Jun 15:29
· 5365 commits to master since this release
v4.2.0
e873743

Added

  • Check execute PMA on instruction frontend
  • Add support for non-contiguous cacheable regions to the PMA checks
  • Provision exponential backoff for AMO SC in L1 D$ miss handler

Changed

  • Several small fixes to get the code running on VCS
  • Fix compressed instruction decoding in tracer
  • Fix privilege bug in performance counters. The counters have always been accessible in user mode.
  • Fix RISC-V PK simulation bug caused due to insufficient time to init the a0 and a1 registers via the bootrom
  • Fix bug in wt_axi_adapter (only appeared when dcache lines were wider than icache lines)
  • Fix potentially long timing path in axi_lite_interface
  • Fix VCS elab warning in load_store_unit
  • Replace PLIC with implementation from lowRISC
  • Re-work interrupt and debug subsystem to associate requests during decode. This improves stability on for non-idempotent loads.
  • Bump fpnew to v0.5.5
  • Bump axi to v0.7.0
  • Bump common_cells to v1.13.1
  • Bump riscv-dbg to v0.1
  • Improve FPU pipelining and timing around scoreboard
  • Reworked the axilite to PLIC shim for OpenPiton+Ariane
  • Remove in and out aliases for AXI interfaces
  • Fix small issues with DC synthesis
  • Fix wrong dirtying of sd flag in mstatus
  • Synthesis fix for Vivado 2018.3
  • Clean-up instruction front-end, small IPC improvement
  • Move to Verilator 4.014
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