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[BUG] When taking a synchronous exception, bit 6 (sync_exc_seen) should be set in the CPUCTRL CSR (0x7C0) #177

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LeeHoff opened this issue Dec 11, 2023 · 1 comment
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[BUG] When taking a synchronous exception, bit 6 (sync_exc_seen) should be set in the CPUCTRL CSR (0x7C0) #177

LeeHoff opened this issue Dec 11, 2023 · 1 comment
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@szbieg

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@LeeHoff
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LeeHoff commented Dec 11, 2023

Bug Description

With the updated reference model, running debug_test with USE_ISS=YES, the reference model sets bit 6 sync_exc_seen in the cpuctrl (0x7c0) register.
This CSR is not implemented in the RTL, but it is in the CVE2 spec.
szbieg added a commit to NXP/openhwgroup-cve2 that referenced this issue Jan 24, 2024
@szbieg
[rtl] restore read/write logic for CSR_CPUCTRL
beefd93 
solves openhwgroup#177

Signed-off-by: Szymon Bieganski <[email protected]>
@szbieg szbieg mentioned this issue Jan 24, 2024
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@davideschiavone
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@christian-herber-nxp , do we want this RTL register? is it only for simulation? if so we can do "ifndef SYNTHESIS", or do we want to remove it from the ISS?

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fix/restore_csrcpuctrl NXP/openhwgroup-cve2
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@davideschiavone @LeeHoff @szbieg