🔖 Release v0.5.3

openhwgroup · May 31, 2019 · 63ca354 · 63ca354
2 parents 71004d2 + 6fbe332
commit 63ca354
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diff --git a/docs/CHANGELOG.md b/docs/CHANGELOG.md
@@ -12,7 +12,12 @@ In this sense, we interpret the "Public API" of a hardware module as its port/pa
 ### Changed
 ### Fixed
 
-## [0.5.1] - 2019-05-31
+## [0.5.3] - 2019-05-31
+
+### Fixed
+- ips_list.yml entry for updated common_cells
+
+## [0.5.2] - 2019-05-31
 
 ### Fixed
 - Internal pipeline bypass in cast unit

diff --git a/ips_list.yml b/ips_list.yml
@@ -19,7 +19,7 @@
 #
 
 common_cells:
-  commit: master
+  commit: 0b8c10c21c9f810509bbd7bf86cfbdc4e6626c8e
   domain: [soc, cluster]
 
 fpu_div_sqrt_mvp: