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    291 repositories

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •48•49•19•6•Updated Sep 30, 2024Sep 30, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •140•500•28•7•Updated Sep 30, 2024Sep 30, 2024

    • chimera

      Public
      Python
      •
      Other
      •1•7•9•2•Updated Sep 30, 2024Sep 30, 2024

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •20•123•10•3•Updated Sep 28, 2024Sep 28, 2024

    • dyn_spm

      Public
      SystemVerilog
      •
      Other
      •0•2•1•0•Updated Sep 28, 2024Sep 28, 2024

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •2•10•0•0•Updated Sep 27, 2024Sep 27, 2024

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •18•18•1•5•Updated Sep 27, 2024Sep 27, 2024

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •39•184•5•20•Updated Sep 27, 2024Sep 27, 2024

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •2•18•1•2•Updated Sep 27, 2024Sep 27, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •675•15•1•7•Updated Sep 27, 2024Sep 27, 2024

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •13•4•0•6•Updated Sep 27, 2024Sep 27, 2024

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •113•12•0•4•Updated Sep 27, 2024Sep 27, 2024

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •44•266•3•7•Updated Sep 27, 2024Sep 27, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •26•88•7•8•Updated Sep 26, 2024Sep 26, 2024

    • register_interface

      Public
      Generic Register Interface (contains various adapters)
      SystemVerilog
      •
      Other
      •24•95•1•0•Updated Sep 25, 2024Sep 25, 2024

    • pulp-linux

      Public
      Build GNU/Linux for various PULP/Cheshire-based systems.
      C
      •0•3•4•0•Updated Sep 24, 2024Sep 24, 2024

    • ITA

      Public
      SystemVerilog
      •
      Other
      •2•9•0•1•Updated Sep 24, 2024Sep 24, 2024

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •126•356•57•10•Updated Sep 19, 2024Sep 19, 2024

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •15•67•1•1•Updated Sep 19, 2024Sep 19, 2024

    • hwpe-doc

      Public
      Specification and documentation for HWPEs
      Python
      •2•7•2•0•Updated Sep 17, 2024Sep 17, 2024

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •752•1•0•1•Updated Sep 16, 2024Sep 16, 2024

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•55•4•3•Updated Sep 16, 2024Sep 16, 2024

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •1•9•0•3•Updated Sep 16, 2024Sep 16, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•8•0•2•Updated Sep 12, 2024Sep 12, 2024

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •11•15•7•0•Updated Sep 12, 2024Sep 12, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •15•25•4•3•Updated Sep 12, 2024Sep 12, 2024

    • pulp-actions

      Public
      Python
      •
      Apache License 2.0
      •3•7•1•0•Updated Sep 11, 2024Sep 11, 2024

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •15•18•2•8•Updated Sep 10, 2024Sep 10, 2024

    • cheshire-ihp130-o

      Public
      Tcl
      •
      Other
      •4•23•1•0•Updated Sep 10, 2024Sep 10, 2024

    • axi_vga

      Public
      SystemVerilog
      •
      Other
      •1•2•0•0•Updated Sep 10, 2024Sep 10, 2024