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    293 repositories

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •3•22•0•0•Updated Nov 18, 2024Nov 18, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •28•91•7•8•Updated Nov 18, 2024Nov 18, 2024

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •47•199•7•19•Updated Nov 18, 2024Nov 18, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •144•518•30•8•Updated Nov 18, 2024Nov 18, 2024

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •132•376•65•10•Updated Nov 15, 2024Nov 15, 2024

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •267•1.1k•43•17•Updated Nov 15, 2024Nov 15, 2024

    • chimera-sdk

      Public
      Python
      •
      Apache License 2.0
      •1•2•4•0•Updated Nov 15, 2024Nov 15, 2024

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •19•75•1•2•Updated Nov 15, 2024Nov 15, 2024

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •13•73•13•6•Updated Nov 15, 2024Nov 15, 2024

    • chimera

      Public
      Python
      •
      Other
      •2•9•9•1•Updated Nov 15, 2024Nov 15, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•8•0•2•Updated Nov 14, 2024Nov 14, 2024

    • llvm-project

      Public
      12k•6•7•1•Updated Nov 14, 2024Nov 14, 2024

    • Deeploy

      Public
      ONNX-to-C Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •7•14•1•3•Updated Nov 14, 2024Nov 14, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •691•16•1•8•Updated Nov 14, 2024Nov 14, 2024

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•56•4•5•Updated Nov 13, 2024Nov 13, 2024

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •34•35•6•4•Updated Nov 13, 2024Nov 13, 2024

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •45•275•4•7•Updated Nov 11, 2024Nov 11, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •16•28•4•3•Updated Nov 11, 2024Nov 11, 2024

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      riscvdebug
      SystemVerilog
      •
      Other
      •75•224•29•6•Updated Nov 11, 2024Nov 11, 2024

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •1•1•4•3•Updated Nov 11, 2024Nov 11, 2024

    • redmule

      Public
      SystemVerilog
      •
      Other
      •12•36•1•3•Updated Nov 10, 2024Nov 10, 2024

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •12•16•7•1•Updated Nov 8, 2024Nov 8, 2024

    • ManyRVData

      Public
      0•0•0•0•Updated Nov 8, 2024Nov 8, 2024

    • pulp-detector

      Public
      C
      •2•12•1•0•Updated Nov 6, 2024Nov 6, 2024

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •52•51•13•6•Updated Nov 5, 2024Nov 5, 2024

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •1•2•0•6•Updated Nov 5, 2024Nov 5, 2024

    • apb_gpio

      Public
      SystemVerilog
      •
      Other
      •18•8•0•0•Updated Nov 4, 2024Nov 4, 2024

    • ITA

      Public
      SystemVerilog
      •
      Other
      •4•10•0•1•Updated Nov 4, 2024Nov 4, 2024

    • fpu_ss

      Public
      CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
      SystemVerilog
      •
      Other
      •8•9•1•0•Updated Nov 4, 2024Nov 4, 2024

    • regression_tests

      Public
      C
      •16•5•3•1•Updated Nov 4, 2024Nov 4, 2024