This repository contains examples to show of some of the PULP platform tools, specifically:
- Bender: Dependency manager for hardware design projects
- Morty: SystemVerilog pickler, (reads in many SystemVerilog files and combines them into one file)
- SVase: SystemVerilog pre-elaboration tool (simplifies SystemVerilog constructs)
There are 3 examples showing of various SVase passes
- parameter propagation
- generate unrolling
- constant function resolving
The most exciting example combines the above mentioned tools together with SV2V (SystemVerilog to Verilog converter).
It shows how you can use the PULP System-on-Chip platform Cheshire to configure cores, peripherals and so on and then bring it to a form where it can be read into Yosys, the open-source synthesis tool.
Here you can see an architectural drawing of Cheshire. The grayed-out elements have not been configured in this example flow.
Important: Here we omit technology-dependent files, especially SRAM macros. If you want to use Cheshire, you will likely also want to map the SRAMs to something useful. An example of a fully functional design using Cheshire are Iguana and Basilisk