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[hardware] Break path to enable of the clk gating explicit cell
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mp-17 committed Sep 8, 2023
1 parent 87680ff commit bccb9dd
Showing 1 changed file with 14 additions and 11 deletions.
25 changes: 14 additions & 11 deletions hardware/src/lane/vmfpu.sv
Original file line number Diff line number Diff line change
Expand Up @@ -112,10 +112,11 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;

// Do we have a vector instruction being processed?
vfu_operation_t vinsn_processing_d, vinsn_processing_q;
logic vinsn_processing_valid;
assign vinsn_processing_d = vinsn_queue_d.vinsn[vinsn_queue_d.processing_pnt];
assign vinsn_processing_q = vinsn_queue_q.vinsn[vinsn_queue_q.processing_pnt];
assign vinsn_processing_valid = (vinsn_queue_q.processing_cnt != '0);
logic vinsn_processing_d_valid, vinsn_processing_q_valid;
assign vinsn_processing_d = vinsn_queue_d.vinsn[vinsn_queue_d.processing_pnt];
assign vinsn_processing_q = vinsn_queue_q.vinsn[vinsn_queue_q.processing_pnt];
assign vinsn_processing_d_valid = (vinsn_queue_d.processing_cnt != '0);
assign vinsn_processing_q_valid = (vinsn_queue_q.processing_cnt != '0);

// Do we have a vector instruction with results being committed?
vfu_operation_t vinsn_commit;
Expand Down Expand Up @@ -283,21 +284,21 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
//////////////////

// Clock-gate for the multipliers
logic clkgate_en, clk_i_gated;
logic clkgate_en_d, clkgate_en_q, clk_i_gated;

`ifdef GF22
clk_gating_gf22
`else
clk_gating_generic
`endif
i_simd_mul_manual_clk_gate (
.CLK(clk_i ),
.TE (1'b0 ),
.E (clkgate_en ),
.Z (clk_i_gated)
.CLK(clk_i ),
.TE (1'b0 ),
.E (clkgate_en_q),
.Z (clk_i_gated )
);

assign clkgate_en = vinsn_processing_valid & (vinsn_processing_q.op inside {[VMUL:VSMUL]});
assign clkgate_en_d = vinsn_processing_d_valid & (vinsn_processing_d.op inside {[VMUL:VSMUL]});

elen_t [3:0] vmul_simd_result;
logic [3:0] vmul_simd_in_valid;
Expand Down Expand Up @@ -1315,7 +1316,7 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
// If we are about to issue an instruction while another one is processing,
// issue only if the new instruction is slower than the previous one
latency_problem_d = vinsn_issue_lat_d < vinsn_processing_lat_d;
latency_stall = vinsn_issue_valid & vinsn_processing_valid & latency_problem_q;
latency_stall = vinsn_issue_valid & vinsn_processing_q_valid & latency_problem_q;

operand_a = (vinsn_issue_q.op == VFRDIV) ? scalar_op : mfpu_operand_i[1]; // vs2
operand_b = (vinsn_issue_q.use_scalar_op && vinsn_issue_q.op != VFRDIV)
Expand Down Expand Up @@ -2218,6 +2219,7 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
intra_op_rx_cnt_q <= '0;
osum_issue_cnt_q <= '0;
mfpu_vxsat_q <= '0;
clkgate_en_q <= 1'b0;
end else begin
issue_cnt_q <= issue_cnt_d;
to_process_cnt_q <= to_process_cnt_d;
Expand All @@ -2241,6 +2243,7 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
intra_op_rx_cnt_q <= intra_op_rx_cnt_d;
osum_issue_cnt_q <= osum_issue_cnt_d;
mfpu_vxsat_q <= mfpu_vxsat_d;
clkgate_en_q <= clkgate_en_d;
end
end

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