axi: Upgrade to v0.39.1

Signed-off-by: Nils Wistoff <[email protected]>

Makefile

@@ -182,6 +182,7 @@ src :=  core/include/$(target)_config_pkg.sv
         vendor/pulp-platform/axi/src/axi_atop_filter.sv                              \
         vendor/pulp-platform/axi/src/axi_err_slv.sv                                  \
         vendor/pulp-platform/axi/src/axi_mux.sv                                      \
+        vendor/pulp-platform/axi/src/axi_demux_simple.sv                             \
         vendor/pulp-platform/axi/src/axi_demux.sv                                    \
         vendor/pulp-platform/axi/src/axi_xbar.sv                                     \
         vendor/pulp-platform/common_cells/src/cdc_2phase.sv                          \

vendor/pulp-platform/axi/.gitignore

@@ -6,3 +6,4 @@
 /Bender.lock
 /Bender.local
 *.log
+*.wlf

vendor/pulp-platform/axi/CHANGELOG.md

@@ -7,23 +7,79 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## Unreleased
 
+## 0.39.1 - 2023-09-05
+
 ### Added
-- Add `axi_channel_compare.sv`: Non-synthesizable module comparing two AXI channels of the same type
-- Add `axi_bus_compare` and `axi_slave_compare`; two synthesizable verification IPs meant to be used
-  to compare two AXI buses on an FPGA.
-- Add `axi_lite_from_mem` and `axi_from_mem` acting like SRAMs making AXI4 requests downstream.
-- Add `axi_rw_join` and `axi_rw_split` to split/join AXI buses.
+- `axi_cdc`: Add `SyncStages` parameter.
+- `axi_to_mem_interleaved`: Add interface variant.
+- `axi_burst_splitter`: Expose `id_queue`'s `FULL_BW` parameter.
+- `axi_chan_compare`: Add parameter to allow reordered transactions.
+- Add `AXI_HIGHLIGHT` macro to highlight AXI signals.
+- Add flat port instantiation macros.
+
+### Fixed
+- `axi_test`: Avoid false negatives for misaligned reads in `axi_scoreboard`.
+- `axi_to_detailed_mem`: Ensure proper propagation or `err` and `exokay` signals.
+
+## 0.39.0 - 2023-07-20
+
+### Added
+- Synthesizable IPs:
+  - `axi_bus_compare` and `axi_slave_compare`; two synthesizable verification IPs meant to be used
+    to compare two AXI buses on an FPGA.
+  - `axi_lite_from_mem` and `axi_from_mem` acting like SRAMs making AXI4 requests downstream.
+  - `axi_lite_dw_converter`: Convert the data width of AXI4-Lite transactions. Emits the
+     appropriate amount of downstream transactions to perform the whole requested access.
+  - `axi_rw_join` and `axi_rw_split` to split/join the read and write channels of an AXI bus.
+- `CT`-macros allowing to instantiate AXI structs with custom channel type names.
+- `axi_pkg': Add documentation to `xbar_cfg_t`.
+- Testbench IPs:
+  - `axi_chan_compare.sv`: Non-synthesizable module comparing two AXI channels of the same type
+  - Add `axi_file_master` to `axi_test`, allowing file-based AXI verification approaches.
+  - Add `#_width` functions to `axi_test` returning the width of the AXI channels.
 
 ### Changed
-- `axi_demux`: Replace FIFO between AW and W channel by a register plus a counter.  This prevents
-  AWs from being issued to one master port while Ws from another burst are ongoing to another
-  master port.  This is required to prevents deadlocks due to circular waits downstream.
-- `axi_xbar`: Add parameter `PipelineStages` to `axi_pkg::xbar_cfg_t`.  This adds `axi_multicuts`
-  in the crossed connections in the xbar between the demuxes and muxes.
-- `axi_pkg`: Add documentation to `xbar_cfg_t`.
+- Synthesizable IPs:
+  - `axi_demux`: Replace FIFO between AW and W channel by a register plus a counter.  This prevents
+    AWs from being issued to one master port while Ws from another burst are ongoing to another
+    master port.  This is required to prevents deadlocks due to circular waits downstream. Removes
+    `FallThrough` parameter from `axi_demux`.
+  - Split the `axi_demux` logic and timing decoupling. A new module called `axi_demux_simple` contains
+    the core logic.
+  - `axi_dw_downsizer` uses `axi_pkg::RESP_EXOKAY` as a default value.
+  - Simplify the `casez` in `axi_id_remap`.
+  - Add optional explicit mapping to the `axi_id_serialize` module.
+  - Expand `axi_to_mem` to `axi_to_detailed_mem` exposing all of AXI's side-signals; namely `id`, `user`,
+    `cache`, `prot`, `qos`, `region`, `atop`. Add possibility to inject `err` and `exokay`.
+  - `axi_xbar`: Add parameter `PipelineStages` to `axi_pkg::xbar_cfg_t`. This adds `axi_multicuts`
+    in the crossed connections in the `xbar` between the *demuxes* and *muxes*. Improve inline
+    documentation.
+  - Move `mem_to_banks` to `common_cells`.
+- `axi_pkg`: Improve for better compatibility with *Vivado*.
+- `axi_test:
+  - `axi_lite_rand_slave`: `R` response field is now randomized.
+  - Remove excessive prints from random master and slave.
+  - Properly size-align the address.
+- `axi_pkg`: Define `localparams` to define AXI type widths.
+- Update `common_cells` from version `v1.26.0` to `v1.27.0`.
+- Tooling:
+  - Use `pulp-platform/pulp-actions/gitlab-ci@v2` in the GitHub CI to communicate with the internal CI.
+  - Bump `DC Shell version` from `2019.12` to `2022.03`
+  - No longer check *ModelSim* versions `10.7e` and `2021.3`, add `2022.3`.
+  - More thorough verification runs for the `xbar`.
+  - Start transitioning from shell script to Makefile to run simulations.
+- Use `scripts/update_authors` to update authors, slight manual fixes performed.
 
 ### Fixed
+- `axi_to_mem_banked`: Reduce hardware by properly setting `UniqueIds`.
+- `axi_to_mem_interleaved` and `axi_to_mem_split` properly instantiates a demultiplexer now.
+  Adds `test_i` port for DFT.
 
+### Breaking Changes
+There are breaking changes between `v0.38.0` and `v0.39.0`:
+- `axi_demux`: `FallThrough` parameter was removed.
+- `axi_xbar`: `axi_pkg::xbar_cfg_t` added `PipelineStages` parameter.
+- `axi_to_mem_interleaved` and `axi_to_mem_split`: Added `test_i` input port.
 
 ## 0.38.0 - 2022-09-28