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ci #1992

Triggered via schedule October 29, 2024 02:32
@SamuelRiedelSamuelRiedel
⁠ 7c4b38e
main
Status Success
Total duration 5m 26s
Artifacts –

ci.yml

on: schedule
tc-gcc
26s
tc-gcc
riscv-isa-sim
6s
riscv-isa-sim
tc-llvm
53s
tc-llvm
verilator
7s
verilator
check-control-registers
21s
check-control-registers
check-opcodes
6s
check-opcodes
Matrix: build-apps-gcc
check-bootrom
12s
check-bootrom
Matrix: build-apps-llvm
tc-halide
7s
tc-halide
Matrix: verilator-model
Matrix: build-apps-halide
Matrix: run-apps-gcc
Matrix: run-apps-llvm
unit-test
1m 59s
unit-test
Matrix: run-apps-halide
clean-up
5s
clean-up
Matrix: clean-up-compile-runs
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