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[Verilator] Fix some issues that prevent verilator compiling in CI.
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Aquaticfuller committed Oct 30, 2024
1 parent 49b27a8 commit db006e5
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Showing 3 changed files with 11 additions and 12 deletions.
19 changes: 9 additions & 10 deletions hardware/src/address_scrambler.sv
Original file line number Diff line number Diff line change
Expand Up @@ -9,17 +9,16 @@
// Author: Samuel Riedel <[email protected]>

module address_scrambler
import mempool_pkg::*;
#(
parameter int unsigned AddrWidth = 32,
parameter int unsigned ByteOffset = 2,
parameter int unsigned NumTiles = 2,
parameter int unsigned NumTilesPerDma = 16,
parameter int unsigned NumBanksPerTile = 2,
parameter bit Bypass = 0,
parameter int unsigned SeqMemSizePerTile = 4*1024,
parameter addr_t TCDMBaseAddr = 32'b0,
parameter logic [31:0] TCDMMask = '1 << 28
parameter int unsigned AddrWidth = 32,
parameter int unsigned ByteOffset = 2,
parameter int unsigned NumTiles = 2,
parameter int unsigned NumTilesPerDma = 16,
parameter int unsigned NumBanksPerTile = 2,
parameter bit Bypass = 0,
parameter int unsigned SeqMemSizePerTile = 4*1024,
parameter logic [AddrWidth-1:0] TCDMBaseAddr = 32'b0,
parameter logic [31:0] TCDMMask = '1 << 28
) (
input logic [AddrWidth-1:0] address_i,
output logic [AddrWidth-1:0] address_o
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2 changes: 1 addition & 1 deletion hardware/src/mempool_group_tile_id_remapper.sv
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Expand Up @@ -29,4 +29,4 @@ module mempool_group_tile_id_remapper
`else
assign tile_id_remap_o = tile_id_remap_before;
`endif
endmodule
endmodule
2 changes: 1 addition & 1 deletion hardware/src/mempool_tile_id_remapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -181,4 +181,4 @@ module mempool_tile_id_remapper
// (remote_req_interco_to_xbar_valid[c] ? remote_req_interco_tgt_sel_shift_local[c] :
// (1 + (c % (NumRemotePortsPerTile - 1))));
end
endmodule
endmodule

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