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Add support for the RP1 DSI hardware. Signed-off-by: Nick Hollinghurst <[email protected]> drm/rp1: depends on, instead of select, MFD_RP1 According to kconfig-language.txt [1], select should be used only for "non-visible symbols ... and for symbols with no dependencies". Since MFD_RP1 both is visible and has a dependency, "select" should not be used and "depends on" should be used instead. In particular, this fixes the build of this kernel tree on NixOS, where its kernel config system will try to answer 'M' to as many config as possible. [1] https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html Signed-off-by: Ratchanan Srirattanamet <[email protected]> DRM: rp1: rp1-dsi: Fix escape clock divider and timeouts. Escape clock divider was fixed at 5, which is correct at 800Mbps/lane but increasingly out of spec for higher rates. Compute it correctly. High speed timeout was fixed at 5*512 == 2560 byte-clocks per lane. Compute it conservatively to be 8/7 times the line period (assuming there will be a transition to LP some time during each scanline?) keeping the old value as a lower bound. Increase LPRX TO to 1024, and BTA TO to 0xb00 (same value as in bridge/synopsys/dw-mipi-dsi). (No change to LP_CMD_TIM. To do: compute this correctly.) Signed-off-by: Nick Hollinghurst <[email protected]> drm: rp1: rp1-dsi: Switch to PLL_SYS source for DPI when 8 * lanes > bpp To support 4 lanes, re-parent DPI clock source between DSI byteclock (using the new "variable sources" defined in clk-rp1) and PLL_SYS. This is to cover cases in which byteclock < pixclock <= 200MHz. Tidying: All frequencies now in Hz (not kHz), where DSI speed is now represented by byteclock to simplify arithmetic. Clamp DPI and byte clocks to their legal ranges; fix up HSTX timeout to avoid an unsafe assumption that it would return to LP state for every scanline. Because of RP1's clock topology, the ratio between DSI and DPI clocks may not be exact with 3 or 4 lanes, leading to slightly irregular timings each time DSI switches between HS and LP states. Tweak to inhibit LP during Horizontal BP when sync pulses were requested. Signed-off-by: Nick Hollinghurst <[email protected]> drm: rp1: rp1-dsi: Add DRM_FORMAT_ARGB8888 and DRM_FORMAT_ABGR8888 Android requires this. As the underlying hardware doesn't support alpha blending, we ignore the alpha value. Signed-off-by: Jan Kehren <[email protected]> drivers: drm: rp1-dsi: Implement more DSI options and flags Now implementing: - Per-command selection of LP or HS for commands (previously LP) - EoTp transmission option (previously EoTp was always disabled) - Non-continuous clock option (previously always continuous) - Per-command enabling of ACK request (in command mode only) Make a plausible (and possibly correct) attempt to measure the longest LP command that will fit into vertical blanking lines. DON'T set both "Burst Mode" and "Sync Events" flags together. This is redundant in the standard IP; in this RP1 variant it would enable Sync Pulses but may break with some video timings. Signed-off-by: Nick Hollinghurst <[email protected]>
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