Merge pull request #536 from qjivy/RV32G-format-loadFPRImm

Porting the LoadFPRImmediate
riscv-collab · Apr 8, 2022 · 2569baa · 2569baa
2 parents 6b2b8af + c61b289
commit 2569baa
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Showing 4 changed files with 22 additions and 9 deletions.
diff --git a/src/codegen/riscv32/macro-assembler-riscv32.cc b/src/codegen/riscv32/macro-assembler-riscv32.cc
@@ -1592,7 +1592,7 @@ void TurboAssembler::MultiPush(RegList regs) {
 #define TEST_AND_PUSH_REG(reg)             \
   if (regs.has(reg)) {                     \
     stack_offset -= kSystemPointerSize;    \
-    Sd(reg, MemOperand(sp, stack_offset)); \
+    Sw(reg, MemOperand(sp, stack_offset)); \
     regs.clear(reg);                       \
   }
 
@@ -2371,14 +2371,20 @@ void TurboAssembler::LoadFPRImmediate(FPURegister dst, uint64_t src) {
   } else {
     if (dst == kDoubleRegZero) {
       DCHECK(src == bit_cast<uint64_t>(0.0));
-      fmv_d_x(dst, zero_reg);
+      fcvt_d_w(dst, zero_reg);
       has_double_zero_reg_set_ = true;
       has_single_zero_reg_set_ = false;
     } else {
+      // Todo: need to clear the stack content?
       UseScratchRegisterScope temps(this);
       Register scratch = temps.Acquire();
-      li(scratch, Operand(src));
-      fmv_d_x(dst, scratch);
+      uint32_t low_32 = src & 0xffffffffull;
+      uint32_t up_32 = src >> 32;
+      li(scratch, Operand(static_cast<int32_t>(low_32)));
+      Sw(scratch, MemOperand(sp, 0));
+      li(scratch, Operand(static_cast<int32_t>(up_32)));
+      Sw(scratch, MemOperand(sp, 4));
+      LoadDouble(dst, MemOperand(sp, 0));
     }
   }
 }

diff --git a/src/diagnostics/riscv32/disasm-riscv32.cc b/src/diagnostics/riscv32/disasm-riscv32.cc
@@ -44,6 +44,7 @@ namespace internal {
 // Decoder decodes and disassembles instructions into an output buffer.
 // It uses the converter to convert register names and call destinations into
 // more informative description.
+#define V8_TARGET_ARCH_64_BIT
 class Decoder {
  public:
   Decoder(const disasm::NameConverter& converter,
@@ -2877,6 +2878,7 @@ int Decoder::InstructionDecode(byte* instr_ptr) {
   return instr->InstructionSize();
 }
 
+#undef V8_TARGET_ARCH_64_BIT
 }  // namespace internal
 }  // namespace v8
 

diff --git a/src/execution/riscv32/simulator-riscv32.cc b/src/execution/riscv32/simulator-riscv32.cc
@@ -1499,9 +1499,14 @@ class RiscvDebugger {
   bool GetValue(const char* desc, int64_t* value);
 };
 
-#define UNSUPPORTED()                                                     \
-  printf("Sim: Unsupported instruction. Func:%s Line:%d\n", __FUNCTION__, \
-         __LINE__);                                                       \
+#define UNSUPPORTED()                                                    \
+  v8::base::EmbeddedVector<char, 256> buffer;                            \
+  disasm::NameConverter converter;                                       \
+  disasm::Disassembler dasm(converter);                                  \
+  dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(&instr_));      \
+  printf("Sim: Unsupported instruction. Func:%s Line:%d ", __FUNCTION__, \
+         __LINE__);                                                      \
+  PrintF(" %-44s\n", buffer.begin());                                    \
   base::OS::Abort();
 
 int64_t RiscvDebugger::GetRegisterValue(int regnum) {

diff --git a/src/objects/code.h b/src/objects/code.h
@@ -667,8 +667,8 @@ class Code : public HeapObject {
   static constexpr int kHeaderPaddingSize = (COMPRESS_POINTERS_BOOL ? 12 : 24);
 #elif V8_TARGET_ARCH_RISCV32
   // static constexpr int kHeaderPaddingSize = (COMPRESS_POINTERS_BOOL ? 12 :
-  // 24); static constexpr int kHeaderPaddingSize = (COMPRESS_POINTERS_BOOL ?
-  // 8 : 20);
+  // 24); static constexpr int kHeaderPaddingSize = (COMPRESS_POINTERS_BOOL ? 8
+  // : 20)；
   static constexpr int kHeaderPaddingSize = 12;  // RV32Gtodo
 #else
 #error Unknown architecture.