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Review the usage of TurboAssembler::LoadFPRImmediate for both uint64_t and uint32_t #535

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qjivy opened this issue Apr 2, 2022 · 0 comments
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RV32G Porting to RV32G ISA

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qjivy commented Apr 2, 2022

This issue record the review of TurboAssembler::LoadFPRImmediate.

TurboAssembler::LoadFPRImmediate is used to load the single and double floating porting bits which are passed by uint32_t and uint64_t src.
The 'src' is a immediate that is either from the bit-cast from a float or double number in the macro-assembler, or from value.to_f32_boxed().get_bits() and value.to_f64_boxed().get_bits() in the liftoff-assembler (@LoadConstant).

When porting to RV32G, we can't no-longer use fmv to move 64bit gp-reg to 64bit fp-reg. So for a 0.0 src, we use fcvt_d_x to convert zero_reg to a double positive zero. For a non-zero src, since RISCV hasn't any "move to high 32bit fp-reg" instruction, so we use store-and-load trick.

@qjivy qjivy added the RV32G Porting to RV32G ISA label Apr 2, 2022
@qjivy qjivy self-assigned this Apr 2, 2022
qjivy added a commit to qjivy/v8 that referenced this issue Apr 2, 2022
riscv-collab#535
Also add disassemble logging for the unsupported RV64 inst.
qjivy added a commit to qjivy/v8 that referenced this issue Apr 8, 2022
refer to: riscv-collab#535
Also add disassemble logging for the unsupported RV64 inst.
qjivy added a commit to qjivy/v8 that referenced this issue Apr 8, 2022
 refer to: riscv-collab#535
 Also add disassemble logging for the unsupported RV64 inst.
qjivy added a commit to qjivy/v8 that referenced this issue Apr 8, 2022
 refer to: riscv-collab#535
 Also add disassemble logging for the unsupported RV64 inst.
@qjivy qjivy closed this as completed Apr 19, 2022
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