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This issue record the review of TurboAssembler::LoadFPRImmediate.
TurboAssembler::LoadFPRImmediate is used to load the single and double floating porting bits which are passed by uint32_t and uint64_t src.
The 'src' is a immediate that is either from the bit-cast from a float or double number in the macro-assembler, or from value.to_f32_boxed().get_bits() and value.to_f64_boxed().get_bits() in the liftoff-assembler (@LoadConstant).
When porting to RV32G, we can't no-longer use fmv to move 64bit gp-reg to 64bit fp-reg. So for a 0.0 src, we use fcvt_d_x to convert zero_reg to a double positive zero. For a non-zero src, since RISCV hasn't any "move to high 32bit fp-reg" instruction, so we use store-and-load trick.
The text was updated successfully, but these errors were encountered:
This issue record the review of TurboAssembler::LoadFPRImmediate.
TurboAssembler::LoadFPRImmediate is used to load the single and double floating porting bits which are passed by uint32_t and uint64_t src.
The 'src' is a immediate that is either from the bit-cast from a float or double number in the macro-assembler, or from value.to_f32_boxed().get_bits() and value.to_f64_boxed().get_bits() in the liftoff-assembler (@LoadConstant).
When porting to RV32G, we can't no-longer use fmv to move 64bit gp-reg to 64bit fp-reg. So for a 0.0 src, we use fcvt_d_x to convert zero_reg to a double positive zero. For a non-zero src, since RISCV hasn't any "move to high 32bit fp-reg" instruction, so we use store-and-load trick.
The text was updated successfully, but these errors were encountered: