Merge branch 'riscv:master' into tariqkurd-repo/master

riscv · Mar 8, 2024 · 3ac3a8d · 3ac3a8d
2 parents 20d441d + d3fcce5
commit 3ac3a8d
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diff --git a/README.md b/README.md
@@ -24,7 +24,7 @@ tools and projects like Spike, PK, RISC-V Manual, etc.
 
 This project follows a very specific file structure to define the instruction encodings. All files
 containing instruction encodings start with the prefix `rv`. These files can either be present in
-the root directory (if the instructions have been ratified) of the `unratified` directory. The exact
+the root directory (if the instructions have been ratified) or the `unratified` directory. The exact
 file-naming policy and location is as mentioned below:
 
 1. `rv_x` - contains instructions common within the 32-bit and 64-bit modes of extension X.

diff --git a/constants.py b/constants.py
@@ -220,4 +220,12 @@
     'mop_rr_7',
     'sspush_x1',
     'sspush_x5',
+    'lpad',
+    'bclri.rv32',
+    'bexti.rv32',
+    'binvi.rv32',
+    'bseti.rv32',
+    'zext.h.rv32',
+    'rev8.h.rv32',
+    'rori.rv32',
 ]
diff --git a/csrs.csv b/csrs.csv
@@ -70,6 +70,7 @@
 0x157, "sireg6"
 0x15C, "stopei"
 0x180, "satp"
+0x181, "srmcfg"
 0x5A8, "scontext"
 0x200, "vsstatus"
 0x204, "vsie"

diff --git a/encoding.h b/encoding.h
@@ -141,6 +141,8 @@
 #define MIP_MEIP            (1 << IRQ_M_EXT)
 #define MIP_SGEIP           (1 << IRQ_S_GEXT)
 #define MIP_LCOFIP          (1 << IRQ_LCOF)
+#define MIP_RAS_LOW_PRIO    (1ULL << IRQ_RAS_LOW_PRIO)
+#define MIP_RAS_HIGH_PRIO   (1ULL << IRQ_RAS_HIGH_PRIO)
 
 #define MIP_S_MASK          (MIP_SSIP | MIP_STIP | MIP_SEIP)
 #define MIP_VS_MASK         (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
@@ -168,11 +170,12 @@
 #define MSTATEEN0_CS       0x00000001
 #define MSTATEEN0_FCSR     0x00000002
 #define MSTATEEN0_JVT      0x00000004
+#define MSTATEEN0_PRIV114  0x0080000000000000
 #define MSTATEEN0_HCONTEXT 0x0200000000000000
-#define MSTATEEN0_CD       0x0100000000000000
 #define MSTATEEN0_HENVCFG  0x4000000000000000
 #define MSTATEEN_HSTATEEN  0x8000000000000000
 
+#define MSTATEEN0H_PRIV114  0x00800000
 #define MSTATEEN0H_HCONTEXT 0x02000000
 #define MSTATEEN0H_HENVCFG  0x40000000
 #define MSTATEENH_HSTATEEN  0x80000000
@@ -250,6 +253,15 @@
 #define JVT_MODE   0x3F
 #define JVT_BASE   (~0x3F)
 
+#define HVICTL_VTI    0x40000000
+#define HVICTL_IID    0x003F0000
+#define HVICTL_DPR    0x00000200
+#define HVICTL_IPRIOM 0x00000100
+#define HVICTL_IPRIO  0x000000FF
+
+#define MTOPI_IID   0x0FFF0000
+#define MTOPI_IPRIO 0x000000FF
+
 #define PRV_U 0
 #define PRV_S 1
 #define PRV_M 3
@@ -295,21 +307,23 @@
 #define PMP_NA4   0x10
 #define PMP_NAPOT 0x18
 
-#define IRQ_U_SOFT   0
-#define IRQ_S_SOFT   1
-#define IRQ_VS_SOFT  2
-#define IRQ_M_SOFT   3
-#define IRQ_U_TIMER  4
-#define IRQ_S_TIMER  5
-#define IRQ_VS_TIMER 6
-#define IRQ_M_TIMER  7
-#define IRQ_U_EXT    8
-#define IRQ_S_EXT    9
-#define IRQ_VS_EXT   10
-#define IRQ_M_EXT    11
-#define IRQ_S_GEXT   12
-#define IRQ_COP      12
-#define IRQ_LCOF     13
+#define IRQ_U_SOFT        0
+#define IRQ_S_SOFT        1
+#define IRQ_VS_SOFT       2
+#define IRQ_M_SOFT        3
+#define IRQ_U_TIMER       4
+#define IRQ_S_TIMER       5
+#define IRQ_VS_TIMER      6
+#define IRQ_M_TIMER       7
+#define IRQ_U_EXT         8
+#define IRQ_S_EXT         9
+#define IRQ_VS_EXT        10
+#define IRQ_M_EXT         11
+#define IRQ_S_GEXT        12
+#define IRQ_COP           12
+#define IRQ_LCOF          13
+#define IRQ_RAS_LOW_PRIO  35
+#define IRQ_RAS_HIGH_PRIO 43
 
 /* page table entry (PTE) fields */
 #define PTE_V     0x001 /* Valid */
@@ -330,6 +344,13 @@
 
 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
 
+/* srmcfg CSR fields */
+#define SRMCFG_RCID  0x00000FFF
+#define SRMCFG_MCID  0x0FFF0000
+
+/* software check exception xtval codes */
+#define LANDING_PAD_FAULT 2
+
 #ifdef __riscv
 
 #if __riscv_xlen == 64

diff --git a/rv32_zbb b/rv32_zbb
@@ -1,3 +1,3 @@
-$pseudo_op rv_zbe::pack     zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33 
-$pseudo_op rv64_zbp::grevi  rev8 rd rs1   31..20=0x698 14..12=5 6..0=0x13
-$pseudo_op rv64_zbb::rori   rori rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv_zbe::pack     zext.h.rv32 rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33
+$pseudo_op rv64_zbp::grevi  rev8.rv32 rd rs1   31..20=0x698 14..12=5 6..0=0x13
+$pseudo_op rv64_zbb::rori   rori.rv32 rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
diff --git a/rv32_zbkb b/rv32_zbkb
@@ -1,4 +1,4 @@
 $pseudo_op rv64_zbp::shfli    zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 
 $pseudo_op rv64_zbp::unshfli  unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 
-$pseudo_op rv64_zbb::rori     rori rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_zbp::grevi    rev8 rd rs1   31..20=0x698 14..12=5 6..0=0x13
+$pseudo_op rv64_zbb::rori     rori.rv32 rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv64_zbp::grevi    rev8.rv32 rd rs1   31..20=0x698 14..12=5 6..0=0x13
diff --git a/rv32_zbs b/rv32_zbs
@@ -1,5 +1,5 @@
-$pseudo_op rv64_zbs::bclri bclri rd rs1 31..25=0x24 shamtw 14..12=1 6..2=0x04 1..0=3
-$pseudo_op rv64_zbs::bexti bexti rd rs1 31..25=0x24 shamtw 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_zbs::binvi binvi rd rs1 31..25=0x34 shamtw 14..12=1 6..2=0x04 1..0=3
-$pseudo_op rv64_zbs::bseti bseti rd rs1 31..25=0x14 shamtw 14..12=1 6..2=0x04 1..0=3
+$pseudo_op rv64_zbs::bclri bclri.rv32 rd rs1 31..25=0x24 shamtw 14..12=1 6..2=0x04 1..0=3
+$pseudo_op rv64_zbs::bexti bexti.rv32 rd rs1 31..25=0x24 shamtw 14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv64_zbs::binvi binvi.rv32 rd rs1 31..25=0x34 shamtw 14..12=1 6..2=0x04 1..0=3
+$pseudo_op rv64_zbs::bseti bseti.rv32 rd rs1 31..25=0x14 shamtw 14..12=1 6..2=0x04 1..0=3
 
diff --git a/rv32_zk b/rv32_zk
@@ -1,8 +1,8 @@
 #import zbkb
 $pseudo_op rv64_zbp::shfli    zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 
 $pseudo_op rv64_zbp::unshfli  unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 
-$pseudo_op rv64_zbb::rori     rori rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_zbp::grevi    rev8 rd rs1   31..20=0x698 14..12=5 6..0=0x13
+$pseudo_op rv64_zbb::rori     rori.rv32 rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv64_zbp::grevi    rev8.rv32 rd rs1   31..20=0x698 14..12=5 6..0=0x13
 
 #import zkne
 $import rv32_zkne::aes32esmi

diff --git a/rv32_zkn b/rv32_zkn
@@ -1,8 +1,8 @@
 #import zbkb
 $pseudo_op rv64_zbp::shfli    zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 
 $pseudo_op rv64_zbp::unshfli  unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 
-$pseudo_op rv64_zbb::rori     rori rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_zbp::grevi    rev8 rd rs1   31..20=0x698 14..12=5 6..0=0x13
+$pseudo_op rv64_zbb::rori     rori.rv32 rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv64_zbp::grevi    rev8.rv32 rd rs1   31..20=0x698 14..12=5 6..0=0x13
 
 #import zkne
 $import rv32_zkne::aes32esmi

diff --git a/rv32_zks b/rv32_zks
@@ -1,6 +1,6 @@
 #import zbkb
 $pseudo_op rv64_zbp::shfli    zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 
 $pseudo_op rv64_zbp::unshfli  unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 
-$pseudo_op rv64_zbb::rori     rori rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_zbp::grevi    rev8 rd rs1   31..20=0x698 14..12=5 6..0=0x13
+$pseudo_op rv64_zbb::rori     rori.rv32 rd rs1   31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv64_zbp::grevi    rev8.rv32 rd rs1   31..20=0x698 14..12=5 6..0=0x13
 
diff --git a/unratified/rv64_zacas → rv64_zacas b/unratified/rv64_zacas → rv64_zacas
diff --git a/rv_c b/rv_c
@@ -6,7 +6,7 @@ c.sw rs1_p rs2_p c_uimm7lo c_uimm7hi    1..0=0 15..13=6
 #quadrant 1
 c.nop c_nzimm6hi c_nzimm6lo              1..0=1 15..13=0 11..7=0
 c.addi rd_rs1_n0 c_nzimm6lo c_nzimm6hi   1..0=1 15..13=0
-c.li rd c_imm6lo c_imm6hi                1..0=1 15..13=2
+c.li rd_n0 c_imm6lo c_imm6hi             1..0=1 15..13=2
 c.addi16sp c_nzimm10hi c_nzimm10lo       1..0=1 15..13=3 11..7=2
 c.lui rd_n2 c_nzimm18hi c_nzimm18lo      1..0=1 15..13=3
 c.andi rd_rs1_p c_imm6hi c_imm6lo        1..0=1 15..13=4 11..10=2
@@ -21,10 +21,10 @@ c.bnez rs1_p c_bimm9lo c_bimm9hi         1..0=1 15..13=7
 #quadrant 2
 c.lwsp rd_n0 c_uimm8sphi c_uimm8splo     1..0=2 15..13=2
 c.jr rs1_n0                              1..0=2 15..13=4 12=0 6..2=0
-c.mv rd c_rs2_n0                         1..0=2 15..13=4 12=0              
+c.mv rd_n0 c_rs2_n0                      1..0=2 15..13=4 12=0
 c.ebreak                                 1..0=2 15..13=4 12=1 11..2=0
 c.jalr c_rs1_n0                          1..0=2 15..13=4 12=1 6..2=0
-c.add rd_rs1 c_rs2_n0                    1..0=2 15..13=4 12=1 
+c.add rd_rs1_n0 c_rs2_n0                 1..0=2 15..13=4 12=1
 c.swsp c_rs2 c_uimm8sp_s                 1..0=2 15..13=6
 
 

diff --git a/unratified/rv_zacas → rv_zacas b/unratified/rv_zacas → rv_zacas
diff --git a/unratified/rv_zvbb → rv_zvbb b/unratified/rv_zvbb → rv_zvbb
diff --git a/unratified/rv_zvkg → rv_zvkg b/unratified/rv_zvkg → rv_zvkg
diff --git a/unratified/rv_zvkn → rv_zvkn b/unratified/rv_zvkn → rv_zvkn
diff --git a/unratified/rv_zvkned → rv_zvkned b/unratified/rv_zvkned → rv_zvkned
diff --git a/unratified/rv_zvknha → rv_zvknha b/unratified/rv_zvknha → rv_zvknha
diff --git a/unratified/rv_zvknhb → rv_zvknhb b/unratified/rv_zvknhb → rv_zvknhb
diff --git a/unratified/rv_zvks → rv_zvks b/unratified/rv_zvks → rv_zvks
diff --git a/unratified/rv_zvksed → rv_zvksed b/unratified/rv_zvksed → rv_zvksed
diff --git a/unratified/rv_zvksh → rv_zvksh b/unratified/rv_zvksh → rv_zvksh
diff --git a/unratified/rv128_c b/unratified/rv128_c
@@ -8,7 +8,7 @@ $import rv64_c::c.sd
 $import rv64_c::c.addiw
 
 #quadrant 2
-c.lqsp rd c_uimm10sphi c_uimm10splo     1..0=2 15..13=1
+c.lqsp rd_n0 c_uimm10sphi c_uimm10splo  1..0=2 15..13=1
 $import rv64_c::c.ldsp
 c.sqsp c_rs2 c_uimm10sp_s               1..0=2 15..13=5
 $import rv64_c::c.sdsp
diff --git a/unratified/rv_zicfilp b/unratified/rv_zicfilp
@@ -0,0 +1,2 @@
+# auipc x0 imm20 -> lpad imm20
+$pseudo_op rv_i::auipc lpad imm20 11..7=0 6..2=0x05 1..0=3