Merge pull request gem5#16 from XDUFanYang/rvv-cpu

misc: Update a reasonable OpClass to RVV
rogerchang23424 · Oct 25, 2022 · ccf590e · ccf590e
2 parents f52d6e6 + 129e658
commit ccf590e
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Showing 7 changed files with 448 additions and 406 deletions.
diff --git a/src/arch/riscv/insts/vector.hh b/src/arch/riscv/insts/vector.hh
@@ -479,8 +479,8 @@ class VMaskMergeMicroInst : public VectorArithMicroInst
   public:
     VMaskMergeMicroInst(ExtMachInst extMachInst, uint8_t _dstReg,
         uint8_t _numSrcs)
-        : VectorArithMicroInst("vmask_mv_micro", extMachInst, VectorDummyOp, 0,
-            0)
+        : VectorArithMicroInst("vmask_mv_micro", extMachInst,
+          VectorIntegerArithOp, 0, 0)
     {
         setRegIdxArrays(
             reinterpret_cast<RegIdArrayPtr>(
@@ -548,8 +548,8 @@ class VxsatMicroInst : public VectorArithMicroInst
     bool* vxsat;
   public:
     VxsatMicroInst(bool* Vxsat, ExtMachInst extMachInst)
-        : VectorArithMicroInst("vxsat_micro", extMachInst, VectorDummyOp, 0,
-            0)
+        : VectorArithMicroInst("vxsat_micro", extMachInst,
+          VectorIntegerArithOp, 0, 0)
     {
         vxsat = Vxsat;
     }

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
diff --git a/src/arch/riscv/isa/templates/vector_arith.isa b/src/arch/riscv/isa/templates/vector_arith.isa
@@ -55,7 +55,7 @@ def template VectorIntMacroConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -103,7 +103,7 @@ template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
                                          uint8_t _microVl, uint8_t _microIdx)
     : %(base_class)s("%(mnemonic)s", _machInst,
-                     VectorDummyOp, _microVl, _microIdx)
+                     %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -274,7 +274,7 @@ def template VectorIntWideningMacroConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -328,7 +328,7 @@ template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
         uint8_t _microVl, uint8_t _microIdx)
     : %(base_class)s("%(mnemonic)s", _machInst,
-                     VectorDummyOp, _microVl, _microIdx)
+                     %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -431,7 +431,7 @@ public:
 def template VectorFloatMacroConstructor {{
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -477,7 +477,7 @@ template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
                                          uint8_t _microVl, uint8_t _microIdx)
     : %(base_class)s("%(mnemonic)s", _machInst,
-                     VectorDummyOp, _microVl, _microIdx)
+                     %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -669,7 +669,7 @@ def template ViotaMacroConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -720,7 +720,7 @@ template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
     uint8_t _microVl, uint8_t _microIdx, int* cnt)
     : %(base_class)s("%(mnemonic)s", _machInst,
-                     VectorDummyOp, _microVl, _microIdx)
+                     %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     this->cnt = cnt;
@@ -761,7 +761,7 @@ def template Vector1Vs1VdMaskConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -813,7 +813,7 @@ def template Vector1Vs1RdMaskConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -861,7 +861,7 @@ def template VectorIntMaskMacroConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -913,7 +913,7 @@ template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
                                          uint8_t _microVl, uint8_t _microIdx)
 : %(base_class)s("%(mnemonic)s", _machInst,
-                 VectorDummyOp, _microVl, _microIdx)
+                 %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -969,7 +969,7 @@ def template VectorFloatMaskMacroConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -1020,7 +1020,7 @@ template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
                                          uint8_t _microVl, uint8_t _microIdx)
 : %(base_class)s("%(mnemonic)s", _machInst,
-                 VectorDummyOp, _microVl, _microIdx)
+                 %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -1074,7 +1074,7 @@ public:
 def template VMvWholeMacroConstructor {{
 
 %(class_name)s::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -1164,7 +1164,7 @@ def template VectorMaskConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(set_dest_reg_idx)s;
@@ -1222,7 +1222,7 @@ def template VectorNonSplitConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -1291,7 +1291,7 @@ def template VectorReduceMacroConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -1338,7 +1338,7 @@ template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
                                          uint8_t _microVl, uint8_t _microIdx)
 : %(base_class)s("%(mnemonic)s", _machInst,
-                 VectorDummyOp, _microVl, _microIdx)
+                 %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -1476,7 +1476,7 @@ def template VectorGatherMacroConstructor {{
 
 template<typename ElemType, typename IndexType>
 %(class_name)s<ElemType, IndexType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -1536,7 +1536,7 @@ template<typename ElemType, typename IndexType>
 %(class_name)s<ElemType, IndexType>::%(class_name)s(ExtMachInst _machInst,
     uint8_t _microVl, uint8_t _microIdx)
 : %(base_class)s("%(mnemonic)s", _machInst,
-                 VectorDummyOp, _microVl, _microIdx)
+                 %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     %(set_reg_idx_arr)s;
@@ -1648,7 +1648,7 @@ def template VectorIntVxsatMacroConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -1700,7 +1700,7 @@ template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
     uint8_t _microVl, uint8_t _microIdx, bool* vxsatptr)
     : %(base_class)s("%(mnemonic)s", _machInst,
-                     VectorDummyOp, _microVl, _microIdx)
+                     %(op_class)s, _microVl, _microIdx)
 {
     this->vm = _machInst.vm;
     this->vxsatptr = vxsatptr;

diff --git a/src/arch/riscv/isa/templates/vector_mem.isa b/src/arch/riscv/isa/templates/vector_mem.isa
@@ -28,7 +28,7 @@ public:
 def template VleConstructor {{
 
 %(class_name)s::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -62,7 +62,7 @@ private:
     RegId destRegIdxArr[1];
 public:
     %(class_name)s(ExtMachInst _machInst, uint8_t _microVl, uint8_t _microIdx)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp, _microVl,
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s, _microVl,
                      _microIdx)
     {
         %(set_reg_idx_arr)s;
@@ -181,7 +181,7 @@ Fault
 def template VseConstructor {{
 
 %(class_name)s::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -216,7 +216,7 @@ private:
     RegId destRegIdxArr[0];
 public:
     %(class_name)s(ExtMachInst _machInst, uint8_t _microVl, uint8_t _microIdx)
-        : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp,
+        : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
                          _microVl, _microIdx)
     {
         %(set_reg_idx_arr)s;
@@ -335,7 +335,7 @@ Fault
 def template VlmConstructor {{
 
 %(class_name)s::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -358,7 +358,7 @@ def template VlmConstructor {{
 def template VsmConstructor {{
 
 %(class_name)s::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -612,7 +612,7 @@ Fault
 def template VlStrideConstructor {{
 
 %(class_name)s::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -652,7 +652,7 @@ private:
 public:
     %(class_name)s(ExtMachInst _machInst, uint8_t _regIdx, uint8_t _microIdx,
         uint8_t _microVl)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp,
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
         _regIdx, _microIdx, _microVl)
     {
         %(set_reg_idx_arr)s;
@@ -798,7 +798,7 @@ Fault
 def template VsStrideConstructor {{
 
 %(class_name)s::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -838,7 +838,7 @@ private:
 public:
     %(class_name)s(ExtMachInst _machInst, uint8_t _regIdx, uint8_t _microIdx,
             uint8_t _microVl)
-        : %(base_class)s("%(mnemonic)s""_micro", _machInst, VectorDummyOp,
+        : %(base_class)s("%(mnemonic)s""_micro", _machInst, %(op_class)s,
             _regIdx, _microIdx, _microVl)
     {
         %(set_reg_idx_arr)s;
@@ -946,7 +946,7 @@ def template VlIndexConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -996,7 +996,7 @@ public:
     %(class_name)s(ExtMachInst _machInst,
         uint8_t _vdRegIdx, uint8_t _vdElemIdx,
         uint8_t _vs2RegIdx, uint8_t _vs2ElemIdx)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp,
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
         _vdRegIdx, _vdElemIdx, _vs2RegIdx, _vs2ElemIdx)
     {
         %(set_reg_idx_arr)s;
@@ -1140,7 +1140,7 @@ def template VsIndexConstructor {{
 
 template<typename ElemType>
 %(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp)
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s)
 {
     %(set_reg_idx_arr)s;
     %(constructor)s;
@@ -1190,7 +1190,7 @@ public:
     %(class_name)s(ExtMachInst _machInst,
         uint8_t _vs3RegIdx, uint8_t _vs3ElemIdx,
         uint8_t _vs2RegIdx, uint8_t _vs2ElemIdx)
-    : %(base_class)s("%(mnemonic)s", _machInst, VectorDummyOp,
+    : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
         _vs3RegIdx, _vs3ElemIdx, _vs2RegIdx, _vs2ElemIdx)
     {
         %(set_reg_idx_arr)s;

diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
@@ -55,7 +55,16 @@ class OpClass(Enum):
             'SimdShaSigma3',
             'SimdPredAlu',
             'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite',
-            'IprAccess', 'InstPrefetch', 'VectorDummy'
+            'IprAccess', 'InstPrefetch',
+            'VectorUnitStrideLoad', 'VectorUnitStrideStore',
+            'VectorUnitStrideMaskLoad', 'VectorUnitStrideMaskStore',
+            'VectorStridedLoad', 'VectorStridedStore',
+            'VectorIndexedLoad', 'VectorIndexedStore',
+            'VectorUnitStrideFaultOnlyFirstLoad',
+            'VectorWholeRegisterLoad', 'VectorWholeRegisterStore',
+            'VectorIntegerArith', 'VectorFloatArith', 'VectorFloatConvert',
+            'VectorIntegerReduce', 'VectorFloatReduce',
+            'VectorMisc', 'VectorIntegerExtension', 'VectorConfig'
             ]
 
 class OpDesc(SimObject):

diff --git a/src/cpu/minor/BaseMinorCPU.py b/src/cpu/minor/BaseMinorCPU.py
@@ -177,7 +177,17 @@ class MinorDefaultMiscFU(MinorFU):
     opLat = 1
 
 class MinorDefaultVecFU(MinorFU):
-    opClasses = minorMakeOpClassSet(['VectorDummy'])
+    opClasses = minorMakeOpClassSet([
+            'VectorUnitStrideLoad', 'VectorUnitStrideStore',
+            'VectorUnitStrideMaskLoad', 'VectorUnitStrideMaskStore',
+            'VectorStridedLoad', 'VectorStridedStore',
+            'VectorIndexedLoad', 'VectorIndexedStore',
+            'VectorUnitStrideFaultOnlyFirstLoad',
+            'VectorWholeRegisterLoad', 'VectorWholeRegisterStore',
+            'VectorIntegerArith', 'VectorFloatArith', 'VectorFloatConvert',
+            'VectorIntegerReduce', 'VectorFloatReduce',
+            'VectorMisc', 'VectorIntegerExtension', 'VectorConfig'
+        ])
     opLat = 1
 
 class MinorDefaultFUPool(MinorFUPool):