GitHub - rsnikhil/Book_BLang_RISCV: Book to (1) learn BLang (BSV) using a RISC-V example and (2) learn to design a pipelined RISC-V CPU using BSV for HDL coding

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Book to (1) learn BLang (BSV) using a RISC-V example and (2) learn to design a pipelined RISC-V CPU using BSV for HDL coding

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Name		Name	Last commit message	Last commit date
Latest commit History 118 Commits
Code_Extracts		Code_Extracts
Figures		Figures
ch000_front		ch000_front
ch010		ch010
ch020		ch020
ch030		ch030
ch040		ch040
ch050		ch050
ch060		ch060
ch070		ch070
ch080		ch080
ch090		ch090
ch100		ch100
ch110		ch110
ch120		ch120
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ch140		ch140
ch150		ch150
ch160		ch160
ch170		ch170
ch180		ch180
ch190		ch190
ch200		ch200
ch800_apx_resources		ch800_apx_resources
ch850_apx_Why_BSV		ch850_apx_Why_BSV
ch860_apx_Glossary		ch860_apx_Glossary
ch870		ch870
ch880		ch880
ch900_back		ch900_back
courseware		courseware
exercises		exercises
zz_Programs/Test_is_legal_BRANCH.bsv		zz_Programs/Test_is_legal_BRANCH.bsv
.gitignore		.gitignore
Book_BLang_RISCV.tex		Book_BLang_RISCV.tex
Makefile		Makefile
README.txt		README.txt
bibliography.bib		bibliography.bib
blankpage.tex		blankpage.tex

Repository files navigation

This is a non-public repository for development of content that
eventually goes into this public repository:

    https://github.com/rsnikhil/Learn_Bluespec_and_RISCV_Design

Content here includes

* Book: "Learn RISC-V CPU Implementation and BSV" by Rishiyur S. Nikhil
* Accompanying lecture slides and exercises

The Fife and Drum source codes used in the book have a separate
development repo:

    https://github.com/bluespec/Fife