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pin contention - TLE8888 + CS + BT #180
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@ksmola since you did UART recently poke :) |
see table on the bottom of https://github.com/rusefi/rusefi/wiki/Hardware_microRusEfi_wiring |
I'm not following the request. Is this correct? |
The request: The request: |
My key concern is if PE0 or PC13 should be connected to the flash traced called HOLD? I have committed a draft copy. Did I get the correct signal to the correct pin? If they are flipped does that matter? Is the PCB as it's drawn now correct and ready for MFG files? |
Does not matter which one is which, it's GPIO so full programmatic control |
Thanks for the verification. This is routed, so we can close it. |
Before the change, 0.5.1 and older HOLD=PB11=UART3 RX |
TL,DR: do we have ANOTHER set of UART pins exposed on MRE not PC10&PC11?
How do we get MRE to
TLE8888 uses TBD pins which conveniently could be multiplexed to SPI1 or SPI3
SD card ideally should be running on a different SPI to reduce contention. We have complete SPI exposed which uses PC10&PC11
so if PC10 and PC11 is used by SPI for SD, do we have another pair of pins exposed on all the little random vias? if not, what would be the minimal HW change to have uart exposed without sharing pins with SPI?
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