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Rollup merge of #91548 - luojia65:hint-spin-loop-riscv, r=Amanieu
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Add spin_loop hint for RISC-V architecture

This commit uses the PAUSE instruction (rust-lang/stdarch#1262) to implement RISC-V spin loop, and updates `stdarch` submodule to use the merged PAUSE instruction.
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matthiaskrgr authored Dec 11, 2021
2 parents 7fbaf33 + 0ccf58b commit 60b9f31
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Showing 2 changed files with 6 additions and 1 deletion.
5 changes: 5 additions & 0 deletions library/core/src/hint.rs
Original file line number Diff line number Diff line change
Expand Up @@ -137,6 +137,11 @@ pub fn spin_loop() {
unsafe { crate::arch::arm::__yield() };
}
}

#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
{
crate::arch::riscv::pause();
}
}

/// An identity function that *__hints__* to the compiler to be maximally pessimistic about what
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2 changes: 1 addition & 1 deletion library/stdarch
Submodule stdarch updated 39 files
+1 −1 .github/workflows/main.yml
+2 −2 ci/docker/aarch64-unknown-linux-gnu/Dockerfile
+6 −2 ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile
+1 −1 ci/run-docker.sh
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+73 −73 crates/core_arch/avx512f.md
+120 −120 crates/core_arch/src/aarch64/neon/generated.rs
+2 −2 crates/core_arch/src/aarch64/neon/mod.rs
+532 −490 crates/core_arch/src/arm_shared/neon/generated.rs
+1 −2 crates/core_arch/src/arm_shared/neon/mod.rs
+2 −0 crates/core_arch/src/core_arch_docs.md
+14 −0 crates/core_arch/src/mod.rs
+10 −0 crates/core_arch/src/riscv/mod.rs
+3 −3 crates/core_arch/src/simd.rs
+604 −0 crates/core_arch/src/x86/avx512bw.rs
+2,292 −0 crates/core_arch/src/x86/avx512f.rs
+1 −1 crates/core_arch/src/x86/avx512gfni.rs
+3 −5 crates/core_arch/src/x86/sse41.rs
+0 −115 crates/intrinsic-test/missing.txt
+133 −0 crates/intrinsic-test/missing_aarch64.txt
+334 −0 crates/intrinsic-test/missing_arm.txt
+6 −0 crates/intrinsic-test/src/acle_csv_parser.rs
+3 −0 crates/intrinsic-test/src/intrinsic.rs
+53 −31 crates/intrinsic-test/src/main.rs
+16 −1 crates/intrinsic-test/src/types.rs
+1 −0 crates/simd-test-macro/src/lib.rs
+205 −0 crates/std_detect/src/detect/arch/riscv.rs
+21 −0 crates/std_detect/src/detect/error_macros.rs
+7 −0 crates/std_detect/src/detect/mod.rs
+2 −1 crates/std_detect/src/detect/os/freebsd/auxvec.rs
+21 −3 crates/std_detect/src/detect/os/linux/auxvec.rs
+32 −0 crates/std_detect/src/detect/os/linux/cpuinfo.rs
+4 −1 crates/std_detect/src/detect/os/linux/mod.rs
+73 −0 crates/std_detect/src/detect/os/linux/riscv.rs
+1 −0 crates/std_detect/src/lib.rs
+16 −16 crates/stdarch-gen/neon.spec
+9 −9 crates/stdarch-gen/src/main.rs
+2 −0 crates/stdarch-verify/tests/arm.rs
+0 −0 rustfmt.toml

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