Remove target features in VxWokrs RISC-V spec as they are automatical…

…ly added by clang
rust-lang · Sep 25, 2024 · 7533b02 · 7533b02
1 parent 4957eda
commit 7533b02
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diff --git a/compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs b/compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs
@@ -16,7 +16,6 @@ pub(crate) fn target() -> Target {
             cpu: "generic-rv32".into(),
             llvm_abiname: "ilp32d".into(),
             max_atomic_width: Some(32),
-            features: "+m,+a,+f,+d,+c,+zicsr".into(),
             stack_probes: StackProbeType::Inline,
             ..base::vxworks::opts()
         },

diff --git a/compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs b/compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs
@@ -16,7 +16,6 @@ pub(crate) fn target() -> Target {
             cpu: "generic-rv64".into(),
             llvm_abiname: "lp64d".into(),
             max_atomic_width: Some(64),
-            features: "+m,+a,+f,+d,+c,+zicsr".into(),
             stack_probes: StackProbeType::Inline,
             ..base::vxworks::opts()
         },