Set max_atomic_width for AVR to 16

[taiki-e]

This is currently set to 0

rust/compiler/rustc_target/src/spec/avr_gnu_base.rs

Lines 26 to 27 in 90f0b24

	max_atomic_width: Some(0),
	atomic_cas: false,

However, LLVM supports {8,16}-bit atomic load/store on AVR (support for RMW is still quite incomplete and only partially supported).

https://github.com/llvm/llvm-project/blob/llvmorg-15.0.0/llvm/test/CodeGen/AVR/atomics/load8.ll#L5-L13
https://github.com/llvm/llvm-project/blob/llvmorg-15.0.0/llvm/test/CodeGen/AVR/atomics/load16.ll#L3-L12
https://github.com/llvm/llvm-project/blob/llvmorg-15.0.0/llvm/test/CodeGen/AVR/atomics/store.ll#L3-L22

cc #99668

r? @Amanieu

[rustbot]

These commits modify compiler targets.
(See the Target Tier Policy.)

[jonas-schievink]

The generated code disables interrupts, which doesn't seem like an operation that should happen implicitly to me. Do any other LLVM targets do this? AVR has an 8-bit data bus, so it can't support anything beyond 8-bit atomics in hardware.

[taiki-e]

The generated code disables interrupts, which doesn't seem like an operation that should happen implicitly to me.

AFAIK, AVR has no unprivileged mode and is always single-core, so the atomic implementation by disabling interrupts is always valid. (The situation differs somewhat from ARM and RISC-V, which have unprivileged modes.)

That said, I'm open to discarding this PR if it is considered that the compiler should not implicitly generate code to disable interrupts to implement atomics, regardless of the architecture.

Do any other LLVM targets do this?

AFAIK, it is only AVR. (However, I think atomic RMW on MSP430 possibly be implemented in the same way in the future, aside from whether the LLVM should do it.)

AVR has an 8-bit data bus, so it can't support anything beyond 8-bit atomics in hardware.

Yeah, we cannot implement 16-bit atomic on AVR without disabling interrupts (or guaranteeing atomicity in an environment-specific way). Although LLVM doesn't seem to consider 8-bit load/store instructions to be atomic either (that may be a bug, but they disable interrupts for both 8-bit and 16-bit atomic load/store).

[Amanieu]

@bors r+

[bors]

📌 Commit c9e83c0 has been approved by Amanieu

It is now in the queue for this repository.