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riscv32 platform support #117874

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Dec 6, 2023
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riscv32 platform support #117874

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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/mod.rs
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Expand Up @@ -1637,6 +1637,7 @@ supported_targets! {
("riscv32imc-esp-espidf", riscv32imc_esp_espidf),
("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
("riscv32imafc-unknown-none-elf", riscv32imafc_unknown_none_elf),
("riscv32imac-unknown-xous-elf", riscv32imac_unknown_xous_elf),
("riscv32gc-unknown-linux-gnu", riscv32gc_unknown_linux_gnu),
("riscv32gc-unknown-linux-musl", riscv32gc_unknown_linux_musl),
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24 changes: 24 additions & 0 deletions compiler/rustc_target/src/spec/targets/riscv32imafc_unknown_none_elf.rs
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use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};

pub fn target() -> Target {
Target {
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
llvm_target: "riscv32".into(),
pointer_width: 32,
arch: "riscv32".into(),

options: TargetOptions {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
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cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
llvm_abiname: "ilp32f".into(),
features: "+m,+a,+c,+f".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}
1 change: 1 addition & 0 deletions src/ci/docker/host-x86_64/dist-various-1/Dockerfile
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Expand Up @@ -95,6 +95,7 @@ ENV TARGETS=$TARGETS,thumbv8m.main-none-eabihf
ENV TARGETS=$TARGETS,riscv32i-unknown-none-elf
ENV TARGETS=$TARGETS,riscv32imc-unknown-none-elf
ENV TARGETS=$TARGETS,riscv32imac-unknown-none-elf
ENV TARGETS=$TARGETS,riscv32imafc-unknown-none-elf
ENV TARGETS=$TARGETS,riscv64imac-unknown-none-elf
ENV TARGETS=$TARGETS,riscv64gc-unknown-none-elf
ENV TARGETS=$TARGETS,armebv7r-none-eabi
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1 change: 1 addition & 0 deletions src/doc/rustc/src/SUMMARY.md
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Expand Up @@ -45,6 +45,7 @@
- [nvptx64-nvidia-cuda](platform-support/nvptx64-nvidia-cuda.md)
- [powerpc64-ibm-aix](platform-support/aix.md)
- [riscv32imac-unknown-xous-elf](platform-support/riscv32imac-unknown-xous-elf.md)
- [riscv32*-unknown-none-elf](platform-support/riscv32imac-unknown-none-elf.md)
- [sparc-unknown-none-elf](./platform-support/sparc-unknown-none-elf.md)
- [*-pc-windows-gnullvm](platform-support/pc-windows-gnullvm.md)
- [\*-nto-qnx-\*](platform-support/nto-qnx.md)
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9 changes: 5 additions & 4 deletions src/doc/rustc/src/platform-support.md
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Expand Up @@ -159,9 +159,9 @@ target | std | notes
[`loongarch64-unknown-none`](platform-support/loongarch-none.md) | * | | LoongArch64 Bare-metal (LP64D ABI)
[`loongarch64-unknown-none-softfloat`](platform-support/loongarch-none.md) | * | | LoongArch64 Bare-metal (LP64S ABI)
[`nvptx64-nvidia-cuda`](platform-support/nvptx64-nvidia-cuda.md) | * | --emit=asm generates PTX code that [runs on NVIDIA GPUs]
`riscv32i-unknown-none-elf` | * | Bare RISC-V (RV32I ISA)
`riscv32imac-unknown-none-elf` | * | Bare RISC-V (RV32IMAC ISA)
`riscv32imc-unknown-none-elf` | * | Bare RISC-V (RV32IMC ISA)
[`riscv32imac-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAC ISA)
[`riscv32i-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32I ISA)
[`riscv32imc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMC ISA)
`riscv64gc-unknown-none-elf` | * | Bare RISC-V (RV64IMAFDC ISA)
`riscv64imac-unknown-none-elf` | * | Bare RISC-V (RV64IMAC ISA)
`sparc64-unknown-linux-gnu` | ✓ | SPARC Linux (kernel 4.4, glibc 2.23)
Expand Down Expand Up @@ -314,7 +314,8 @@ target | std | host | notes
[`powerpc64-ibm-aix`](platform-support/aix.md) | ? | | 64-bit AIX (7.2 and newer)
`riscv32gc-unknown-linux-gnu` | | | RISC-V Linux (kernel 5.4, glibc 2.33)
`riscv32gc-unknown-linux-musl` | | | RISC-V Linux (kernel 5.4, musl + RISCV32 support patches)
`riscv32im-unknown-none-elf` | * | | Bare RISC-V (RV32IM ISA)
[`riscv32imafc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAFC ISA)
[`riscv32im-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | | Bare RISC-V (RV32IM ISA)
[`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? | | RISC-V Xous (RV32IMAC ISA)
[`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
[`riscv32imac-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
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1 change: 1 addition & 0 deletions src/doc/rustc/src/platform-support/riscv32i-unknown-none-elf.md
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riscv32imac-unknown-none-elf.md
1 change: 1 addition & 0 deletions src/doc/rustc/src/platform-support/riscv32im-unknown-none-elf.md
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riscv32imac-unknown-none-elf.md
34 changes: 34 additions & 0 deletions src/doc/rustc/src/platform-support/riscv32imac-unknown-none-elf.md
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# `riscv32{i,im,imc,imac,imafc}-unknown-none-elf`

**Tier: 2/3**

Bare-metal target for RISC-V CPUs with the RV32I, RV32IM, RV32IMC, RV32IMAFC and RV32IMAC ISAs.

## Target maintainers

* Rust Embedded Working Group, [RISC-V team](https://github.com/rust-embedded/wg#the-risc-v-team)

## Requirements

The target is cross-compiled, and uses static linking. No external toolchain
is required and the default `rust-lld` linker works, but you must specify
a linker script. The [`riscv-rt`] crate provides a suitable one. The
[`riscv-rust-quickstart`] repository gives an example of an RV32 project.

[`riscv-rt`]: https://crates.io/crates/riscv-rt
[`riscv-rust-quickstart`]: https://github.com/riscv-rust/riscv-rust-quickstart

## Building the target

This target is included in Rust and can be installed via `rustup`.

## Testing

This is a cross-compiled no-std target, which must be run either in a simulator
or by programming them onto suitable hardware. It is not possible to run the
Rust testsuite on this target.

## Cross-compilation toolchains and C code

This target supports C code. If interlinking with C or C++, you may need to use
riscv64-unknown-elf-gcc as a linker instead of rust-lld.
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1 change: 1 addition & 0 deletions src/doc/rustc/src/platform-support/riscv32imafc-unknown-none-elf.md
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riscv32imac-unknown-none-elf.md
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I did not know about this quirk of mdbook that turns it into a symlink. Cute.

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Hmm, wait, the table links to the same file... no, I think this is just not getting used at all...?

@MabezDev Was this intentional?

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Oops, you're right. I will fix that now.

1 change: 1 addition & 0 deletions src/doc/rustc/src/platform-support/riscv32imc-unknown-none-elf.md
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riscv32imac-unknown-none-elf.md
1 change: 1 addition & 0 deletions src/tools/build-manifest/src/main.rs
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Expand Up @@ -124,6 +124,7 @@ static TARGETS: &[&str] = &[
"riscv32im-unknown-none-elf",
"riscv32imc-unknown-none-elf",
"riscv32imac-unknown-none-elf",
"riscv32imafc-unknown-none-elf",
"riscv32gc-unknown-linux-gnu",
"riscv64imac-unknown-none-elf",
"riscv64gc-unknown-hermit",
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