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Support clobber_abi and vector registers (clobber-only) in PowerPC inline assembly #131341
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// v0-v19 | ||
// FIXME: PPC32 SysV ABI does not mention vector registers processing. | ||
// https://refspecs.linuxfoundation.org/elf/elfspec_ppc.pdf | ||
v0, v1, v2, v3, v4, v5, v6, v7, | ||
v8, v9, v10, v11, v12, v13, v14, | ||
v15, v16, v17, v18, v19, |
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The reason I did not treat these as clobbered only on PPC64 is that the PPC32 ABI document I referenced was released at a time when Altivec/VMX did not exist, and I thought it might not reflect the final status of the PPC32 ABI.
In a similar case, the early ABI documents for s390x (e.g., the one mentioned here) do not mention vector registers, but the ABI documents since the addition of vector facility mention them and all are treated as volatile.
// FIXME: In AIX, v20-v31 are reserved or nonvolatile depending on the mode. | ||
// https://www.ibm.com/docs/en/aix/7.3?topic=concepts-aix-vector-programming |
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@ecnelises @bzEq: Is the default in Rust the default Vector enabled mode, as the name implies? Also, is there a way provided for the compiler to understand the current mode?
(If the first is yes and the second is no, it would be sufficient to simply reject the use of v20-v31 as reserved. If the first is no, this code is fine as is.)
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It should refer to vec-extabi
, which is the default. See
abi: "vec-extabi".into(), |
Opened #131551 (which is based on this PR) to implement this. (I'm not sticking to whether that PR should be a separate PR or part of this PR, so I can merge that PR into this PR if needed.) |
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In fact, |
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Updated to check ABI in v20-v31 for AIX, and update def_regs to reflect the fact that r13 is not reserved on 32-bit AIX (see also LLVM's getReservedRegs). (32-bit AIX is currently not supported by rustc, although) |
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| All | `r19` (Hexagon), `x19` (Arm64EC) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. | | ||
| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. | | ||
| MIPS | `$1` or `$at` | Reserved for assembler. | | ||
| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. | | ||
| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. | | ||
| MIPS | `$ra` | Return address cannot be used as inputs or outputs. | | ||
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. | | ||
| PowerPC | `$r2`, `$r13` | These are system reserved registers. | | ||
| PowerPC | `$r29`, `$r30` | These are used internally by LLVM. | |
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It's ok to not support these two registers conservasively IMO, might rephrase to These might be used as base pointer inside LLVM
.
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I found a line that collectively describes registers in the same situation, so I moved these two there.
| All | `r19` (Hexagon), `r29` (PowerPC), `r30` (PowerPC), `x19` (Arm64EC) | These are used internally by LLVM as "base pointer" for functions with complex stack frames. | |
| All | `r19` (Hexagon), `x19` (Arm64EC) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. | | ||
| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. | | ||
| MIPS | `$1` or `$at` | Reserved for assembler. | | ||
| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. | | ||
| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. | | ||
| MIPS | `$ra` | Return address cannot be used as inputs or outputs. | | ||
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. | | ||
| PowerPC | `$r2`, `$r13` | These are system reserved registers. | |
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nit: Separate r2
and r13
.
r2
is used as TOC pointer.
r13
is system reserved register.
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Those explanations were just copied from the error message, but AFAIK r2 is used as a thread pointer in the PPC32 SVR4 ABI (Linux, FreeBSD, NetBSD, OpenBSD), so I think the current explanation is actually fine as is.
rust/compiler/rustc_target/src/asm/powerpc.rs
Lines 197 to 198 in d30a53e
#error = ["r2", "2"] => | |
"r2 is a system reserved register and cannot be used as an operand for inline asm", |
| All | `r19` (Hexagon), `x19` (Arm64EC) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. | | ||
| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. | | ||
| MIPS | `$1` or `$at` | Reserved for assembler. | | ||
| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. | | ||
| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. | | ||
| MIPS | `$ra` | Return address cannot be used as inputs or outputs. | | ||
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. | | ||
| PowerPC | `$r2`, `$r13` | These are system reserved registers. | | ||
| PowerPC | `$r29`, `$r30` | These are used internally by LLVM. | | ||
| PowerPC | `lr` | The link register cannot be used as an input or output. | |
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I think xer
should be not supported either and should occupy a line after lr
.
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Currently, xer
is supported as a clobber-only register.
| PowerPC | `xer` | `xer` | Only clobbers | |
See https://rust-lang.zulipchat.com/#narrow/stream/216763-project-inline-asm/topic/preserve_flags.20on.20OpenPower.2FPowerPC.3F/near/251292056 for more context.
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Cool, I thought these lines are for input or output operands. It makes sense xer
as clobber operand since there are instructions changing the ca
bit of xer
.
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I have no more comments and LGTM. |
This supports
clobber_abi
which is one of the requirements of stabilization mentioned in #93335.This basically does a similar thing I did in #130630 to implement
clobber_abi
for s390x, but for powerpc/powerpc64/powerpc64le.vreg
) as clobber-only, which need to support clobbering of them to implementclobber_abi
.vreg
should be able to accept#[repr(simd)]
types as input/output if the unstablealtivec
target feature is enabled, butcore::arch::{powerpc,powerpc64}
vector types,#[repr(simd)]
, andcore::simd
are all unstable, so the fact that this is currently a clobber-only should not be considered a blocker of clobber_abi implementation or stabilization. So I have not implemented it in this PR.Refs:
If I understand the above four ABI documentations correctly, except for the PPC32 SysV's VR (Vector Registers) and 32-bit AIX (currently not supported by rustc)'s r13, there does not appear to be important differences in terms of implementing
clobber_abi
:The above four ABIs are consistent about FPR (0-13: volatile, 14-31: nonvolatile), CR (0-1,5-7: volatile, 2-4: nonvolatile), XER (volatile), and CTR (volatile).
As for GPR, only the registers we are treating as reserved are slightly different
As for FPSCR, volatile in PPC64 ELFv1/AIX, some fields are volatile only in certain situations (rest are volatile) in PPC32 SysV/PPC64 ELFv2.
As for VR (Vector Registers), it is not mentioned in PPC32 SysV, v0-v19 are volatile in both in PPC64 ELF/AIX, v20-v31 are nonvolatile in PPC64 ELF, reserved or nonvolatile depending on the ABI (vec-extabi vs vec-default in LLVM, we are using vec-extabi) in AIX:
I left FIXME comment about PPC32 SysV and added ABI check for AIX.
As for VRSAVE, it is not mentioned in PPC32 SysV, nonvolatile in PPC64 ELFv1, reserved in PPC64 ELFv2/AIX
As for VSCR, it is not mentioned in PPC32 SysV/PPC64 ELFv1, some fields are volatile only in certain situations (rest are volatile) in PPC64 ELFv2, volatile in AIX
We are currently treating r1-r2, r13 (non-32-bit-AIX), r29-r31, LR, CTR, and VRSAVE as reserved.
We are currently not processing anything about FPSCR and VSCR, but I feel those are things that should be processed by
preserves_flags
rather thanclobber_abi
if we need to do something about them. (However, PPCRegisterInfo.td in LLVM does not seem to define anything about them.)Replaces #111335 and #124279
cc @ecnelises @bzEq @lu-zero
r? @Amanieu
@rustbot label +O-PowerPC +A-inline-assembly
Footnotes
callee-saved, according to LLVM and GCC. ↩