-
Notifications
You must be signed in to change notification settings - Fork 12.7k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Add riscv32im-unknown-none-elf built-in target triple. #93749
Conversation
Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @matthewjasper (or someone else) soon. Please see the contribution instructions for more information. |
|
Hello @matthewjasper would you happen to have a chance to look at this change? Or perhaps add in the relevant reviewers? Thanks! @kraj I see you have added similar targets for riscv in the past, would you be able to look over this change as well? Thanks! |
sure |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
lgtm
Update riscv32im-unknown-none-elf to Tier2 support. Downgrade to Tier 3 platform support.
35fac45
to
eae6835
Compare
r? @wesleywiser |
@bors r+ |
I can't agree, I hear about this role for the first time :) |
I'm sorry, I may have added the wrong member. This file shows a risc-v team which I thought you were included in, https://github.com/rust-lang/team/blob/master/teams/risc-v.toml |
Just to clarify, there is a risc-v "notification group" which is used as a list of people who are familiar with a given topic and might be willing to answer questions about it or help with issues related to it. The risc-v notification group was created in rust-lang/team#362. |
@wesleywiser Can you add me to this group as well? I do have interest in RISCV ports as I tinker with it often I can perhaps offer some help. |
Ahhh I see. Thank you for the clarification on that @wesleywiser |
@bors r+ |
📌 Commit eae6835 has been approved by |
⌛ Testing commit eae6835 with merge 9b1ba030c4ea5ab134cad0dd883fefb0dc70af55... |
💥 Test timed out |
@bors retry |
☀️ Test successful - checks-actions |
Finished benchmarking commit (bce19cf): comparison url. Summary: This benchmark run did not return any relevant results. 5 results were found to be statistically significant but too small to be relevant. If you disagree with this performance assessment, please file an issue in rust-lang/rustc-perf. @rustbot label: -perf-regression |
riscv32im-unknown-none-elf
.platform-support.md
to list it as a Tier 3 target.Below are details on how this target meets the requirements for tier 3:
I would be willing to be a target maintainer, though I would appreciate if others with more experience around RISC-V volunteered to help with that as well.
Uses the same naming as the LLVM target, and the same convention as many other bare-metal targets.
I don't believe there is any ambiguity here.
I don't see any legal issues here.
I see no issues with any of the above.
Only relevant to those making approval decisions.
core
andalloc
can be used.std
cannot be used as this is a bare-metal target.Use
--target=x86_64-unknown-none-elf
option to cross compile, just like any target. The target does not support running tests.I don't foresee this being a problem.
No other targets should be affected by the pull request.