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KVM: selftests: Return a value from vcpu_get_reg() instead of using a…
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…n out-param

Return a uint64_t from vcpu_get_reg() instead of having the caller provide
a pointer to storage, as none of the KVM_GET_ONE_REG usage in KVM selftests
accesses a register larger than 64 bits, and vcpu_set_reg() only accepts a
64-bit value.  If a use case comes along that needs to get a register that
is larger than 64 bits, then a utility can be added to assert success and
take a void pointer, but until then, forcing an out param yields ugly code
and prevents feeding the output of vcpu_get_reg() into vcpu_set_reg().

Signed-off-by: Sean Christopherson <[email protected]>
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@sean-jc
sean-jc committed Sep 11, 2024
1 parent b4298ba commit f879c49
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Showing 14 changed files with 77 additions and 77 deletions.
10 changes: 5 additions & 5 deletions tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu)
uint64_t reg_id = raz_wi_reg_ids[i];
uint64_t val;

vcpu_get_reg(vcpu, reg_id, &val);
val = vcpu_get_reg(vcpu, reg_id);
TEST_ASSERT_EQ(val, 0);

/*
Expand All @@ -106,7 +106,7 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu)
*/
vcpu_set_reg(vcpu, reg_id, BAD_ID_REG_VAL);

vcpu_get_reg(vcpu, reg_id, &val);
val = vcpu_get_reg(vcpu, reg_id);
TEST_ASSERT_EQ(val, 0);
}
}
Expand All @@ -126,14 +126,14 @@ static void test_user_raz_invariant(struct kvm_vcpu *vcpu)
uint64_t reg_id = raz_invariant_reg_ids[i];
uint64_t val;

vcpu_get_reg(vcpu, reg_id, &val);
val = vcpu_get_reg(vcpu, reg_id);
TEST_ASSERT_EQ(val, 0);

r = __vcpu_set_reg(vcpu, reg_id, BAD_ID_REG_VAL);
TEST_ASSERT(r < 0 && errno == EINVAL,
"unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);

vcpu_get_reg(vcpu, reg_id, &val);
val = vcpu_get_reg(vcpu, reg_id);
TEST_ASSERT_EQ(val, 0);
}
}
Expand All @@ -144,7 +144,7 @@ static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu)
{
uint64_t val, el0;

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));

el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
return el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY;
Expand Down
4 changes: 2 additions & 2 deletions tools/testing/selftests/kvm/aarch64/debug-exceptions.c
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Original file line number Diff line number Diff line change
Expand Up @@ -501,7 +501,7 @@ void test_single_step_from_userspace(int test_cnt)
TEST_ASSERT(ss_enable, "Unexpected KVM_EXIT_DEBUG");

/* Check if the current pc is expected. */
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &pc);
pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
TEST_ASSERT(!test_pc || pc == test_pc,
"Unexpected pc 0x%lx (expected 0x%lx)",
pc, test_pc);
Expand Down Expand Up @@ -583,7 +583,7 @@ int main(int argc, char *argv[])
uint64_t aa64dfr0;

vm = vm_create_with_one_vcpu(&vcpu, guest_code);
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &aa64dfr0);
aa64dfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1));
__TEST_REQUIRE(debug_version(aa64dfr0) >= 6,
"Armv8 debug architecture not supported.");
kvm_vm_free(vm);
Expand Down
6 changes: 3 additions & 3 deletions tools/testing/selftests/kvm/aarch64/hypercalls.c
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Original file line number Diff line number Diff line change
Expand Up @@ -173,7 +173,7 @@ static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i];

/* First 'read' should be an upper limit of the features supported */
vcpu_get_reg(vcpu, reg_info->reg, &val);
val = vcpu_get_reg(vcpu, reg_info->reg);
TEST_ASSERT(val == FW_REG_ULIMIT_VAL(reg_info->max_feat_bit),
"Expected all the features to be set for reg: 0x%lx; expected: 0x%lx; read: 0x%lx",
reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), val);
Expand All @@ -184,7 +184,7 @@ static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
"Failed to clear all the features of reg: 0x%lx; ret: %d",
reg_info->reg, errno);

vcpu_get_reg(vcpu, reg_info->reg, &val);
val = vcpu_get_reg(vcpu, reg_info->reg);
TEST_ASSERT(val == 0,
"Expected all the features to be cleared for reg: 0x%lx", reg_info->reg);

Expand Down Expand Up @@ -214,7 +214,7 @@ static void test_fw_regs_after_vm_start(struct kvm_vcpu *vcpu)
* Before starting the VM, the test clears all the bits.
* Check if that's still the case.
*/
vcpu_get_reg(vcpu, reg_info->reg, &val);
val = vcpu_get_reg(vcpu, reg_info->reg);
TEST_ASSERT(val == 0,
"Expected all the features to be cleared for reg: 0x%lx",
reg_info->reg);
Expand Down
6 changes: 3 additions & 3 deletions tools/testing/selftests/kvm/aarch64/psci_test.c
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Original file line number Diff line number Diff line change
Expand Up @@ -102,8 +102,8 @@ static void assert_vcpu_reset(struct kvm_vcpu *vcpu)
{
uint64_t obs_pc, obs_x0;

vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &obs_pc);
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0]), &obs_x0);
obs_pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
obs_x0 = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0]));

TEST_ASSERT(obs_pc == CPU_ON_ENTRY_ADDR,
"unexpected target cpu pc: %lx (expected: %lx)",
Expand Down Expand Up @@ -143,7 +143,7 @@ static void host_test_cpu_on(void)
*/
vcpu_power_off(target);

vcpu_get_reg(target, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &target_mpidr);
target_mpidr = vcpu_get_reg(target, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1));
vcpu_args_set(source, 1, target_mpidr & MPIDR_HWID_BITMASK);
enter_guest(source);

Expand Down
18 changes: 9 additions & 9 deletions tools/testing/selftests/kvm/aarch64/set_id_regs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -335,7 +335,7 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
uint64_t mask = ftr_bits->mask;
uint64_t val, new_val, ftr;

vcpu_get_reg(vcpu, reg, &val);
val = vcpu_get_reg(vcpu, reg);
ftr = (val & mask) >> shift;

ftr = get_safe_value(ftr_bits, ftr);
Expand All @@ -345,7 +345,7 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
val |= ftr;

vcpu_set_reg(vcpu, reg, val);
vcpu_get_reg(vcpu, reg, &new_val);
new_val = vcpu_get_reg(vcpu, reg);
TEST_ASSERT_EQ(new_val, val);

return new_val;
Expand All @@ -359,7 +359,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
uint64_t val, old_val, ftr;
int r;

vcpu_get_reg(vcpu, reg, &val);
val = vcpu_get_reg(vcpu, reg);
ftr = (val & mask) >> shift;

ftr = get_invalid_value(ftr_bits, ftr);
Expand All @@ -373,7 +373,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
TEST_ASSERT(r < 0 && errno == EINVAL,
"Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);

vcpu_get_reg(vcpu, reg, &val);
val = vcpu_get_reg(vcpu, reg);
TEST_ASSERT_EQ(val, old_val);
}

Expand Down Expand Up @@ -470,7 +470,7 @@ static void test_clidr(struct kvm_vcpu *vcpu)
uint64_t clidr;
int level;

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), &clidr);
clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));

/* find the first empty level in the cache hierarchy */
for (level = 1; level < 7; level++) {
Expand All @@ -495,7 +495,7 @@ static void test_ctr(struct kvm_vcpu *vcpu)
{
u64 ctr;

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), &ctr);
ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
ctr &= ~CTR_EL0_DIC_MASK;
if (ctr & CTR_EL0_IminLine_MASK)
ctr--;
Expand All @@ -511,7 +511,7 @@ static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
test_clidr(vcpu);
test_ctr(vcpu);

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &val);
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1));
val++;
vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), val);

Expand All @@ -524,7 +524,7 @@ static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encodin
size_t idx = encoding_to_range_idx(encoding);
uint64_t observed;

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding), &observed);
observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
TEST_ASSERT_EQ(test_reg_vals[idx], observed);
}

Expand Down Expand Up @@ -559,7 +559,7 @@ int main(void)
vm = vm_create_with_one_vcpu(&vcpu, guest_code);

/* Check for AARCH64 only system */
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
aarch64_only = (el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY);

Expand Down
19 changes: 9 additions & 10 deletions tools/testing/selftests/kvm/aarch64/vpmu_counter_access.c
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Original file line number Diff line number Diff line change
Expand Up @@ -440,8 +440,7 @@ static void create_vpmu_vm(void *guest_code)
"Failed to create vgic-v3, skipping");

/* Make sure that PMUv3 support is indicated in the ID register */
vcpu_get_reg(vpmu_vm.vcpu,
KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &dfr0);
dfr0 = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1));
pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), dfr0);
TEST_ASSERT(pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF &&
pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP,
Expand Down Expand Up @@ -484,7 +483,7 @@ static void test_create_vpmu_vm_with_pmcr_n(uint64_t pmcr_n, bool expect_fail)
create_vpmu_vm(guest_code);
vcpu = vpmu_vm.vcpu;

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr_orig);
pmcr_orig = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0));
pmcr = pmcr_orig;

/*
Expand All @@ -493,7 +492,7 @@ static void test_create_vpmu_vm_with_pmcr_n(uint64_t pmcr_n, bool expect_fail)
*/
set_pmcr_n(&pmcr, pmcr_n);
vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), pmcr);
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr);
pmcr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0));

if (expect_fail)
TEST_ASSERT(pmcr_orig == pmcr,
Expand Down Expand Up @@ -521,7 +520,7 @@ static void run_access_test(uint64_t pmcr_n)
vcpu = vpmu_vm.vcpu;

/* Save the initial sp to restore them later to run the guest again */
vcpu_get_reg(vcpu, ARM64_CORE_REG(sp_el1), &sp);
sp = vcpu_get_reg(vcpu, ARM64_CORE_REG(sp_el1));

run_vcpu(vcpu, pmcr_n);

Expand Down Expand Up @@ -572,12 +571,12 @@ static void run_pmregs_validity_test(uint64_t pmcr_n)
* Test if the 'set' and 'clr' variants of the registers
* are initialized based on the number of valid counters.
*/
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), &reg_val);
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id));
TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,
"Initial read of set_reg: 0x%llx has unimplemented counters enabled: 0x%lx",
KVM_ARM64_SYS_REG(set_reg_id), reg_val);

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id), &reg_val);
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id));
TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,
"Initial read of clr_reg: 0x%llx has unimplemented counters enabled: 0x%lx",
KVM_ARM64_SYS_REG(clr_reg_id), reg_val);
Expand All @@ -589,12 +588,12 @@ static void run_pmregs_validity_test(uint64_t pmcr_n)
*/
vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), max_counters_mask);

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), &reg_val);
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id));
TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,
"Read of set_reg: 0x%llx has unimplemented counters enabled: 0x%lx",
KVM_ARM64_SYS_REG(set_reg_id), reg_val);

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id), &reg_val);
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id));
TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,
"Read of clr_reg: 0x%llx has unimplemented counters enabled: 0x%lx",
KVM_ARM64_SYS_REG(clr_reg_id), reg_val);
Expand Down Expand Up @@ -625,7 +624,7 @@ static uint64_t get_pmcr_n_limit(void)
uint64_t pmcr;

create_vpmu_vm(guest_code);
vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr);
pmcr = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0));
destroy_vpmu_vm();
return get_pmcr_n(pmcr);
}
Expand Down
6 changes: 4 additions & 2 deletions tools/testing/selftests/kvm/include/kvm_util.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -702,11 +702,13 @@ static inline int __vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t va

return __vcpu_ioctl(vcpu, KVM_SET_ONE_REG, &reg);
}
static inline void vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id, void *addr)
static inline uint64_t vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id)
{
struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)addr };
uint64_t val;
struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)&val };

vcpu_ioctl(vcpu, KVM_GET_ONE_REG, &reg);
return val;
}
static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val)
{
Expand Down
8 changes: 4 additions & 4 deletions tools/testing/selftests/kvm/lib/aarch64/processor.c
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Original file line number Diff line number Diff line change
Expand Up @@ -281,8 +281,8 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init)
*/
vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CPACR_EL1), 3 << 20);

vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL1), &sctlr_el1);
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TCR_EL1), &tcr_el1);
sctlr_el1 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL1));
tcr_el1 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TCR_EL1));

/* Configure base granule size */
switch (vm->mode) {
Expand Down Expand Up @@ -360,8 +360,8 @@ void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
{
uint64_t pstate, pc;

vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate), &pstate);
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &pc);
pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate));
pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));

fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n",
indent, "", pstate, pc);
Expand Down
66 changes: 33 additions & 33 deletions tools/testing/selftests/kvm/lib/riscv/processor.c
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Original file line number Diff line number Diff line change
Expand Up @@ -221,39 +221,39 @@ void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
{
struct kvm_riscv_core core;

vcpu_get_reg(vcpu, RISCV_CORE_REG(mode), &core.mode);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc), &core.regs.pc);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra), &core.regs.ra);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp), &core.regs.sp);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp), &core.regs.gp);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp), &core.regs.tp);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0), &core.regs.t0);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1), &core.regs.t1);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2), &core.regs.t2);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0), &core.regs.s0);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1), &core.regs.s1);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0), &core.regs.a0);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1), &core.regs.a1);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2), &core.regs.a2);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3), &core.regs.a3);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4), &core.regs.a4);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5), &core.regs.a5);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6), &core.regs.a6);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7), &core.regs.a7);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2), &core.regs.s2);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3), &core.regs.s3);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4), &core.regs.s4);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5), &core.regs.s5);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6), &core.regs.s6);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7), &core.regs.s7);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8), &core.regs.s8);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9), &core.regs.s9);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10), &core.regs.s10);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11), &core.regs.s11);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3), &core.regs.t3);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4), &core.regs.t4);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5), &core.regs.t5);
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6), &core.regs.t6);
core.mode = vcpu_get_reg(vcpu, RISCV_CORE_REG(mode));
core.regs.pc = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc));
core.regs.ra = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra));
core.regs.sp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp));
core.regs.gp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp));
core.regs.tp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp));
core.regs.t0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0));
core.regs.t1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1));
core.regs.t2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2));
core.regs.s0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0));
core.regs.s1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1));
core.regs.a0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0));
core.regs.a1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1));
core.regs.a2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2));
core.regs.a3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3));
core.regs.a4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4));
core.regs.a5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5));
core.regs.a6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6));
core.regs.a7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7));
core.regs.s2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2));
core.regs.s3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3));
core.regs.s4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4));
core.regs.s5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5));
core.regs.s6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6));
core.regs.s7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7));
core.regs.s8 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8));
core.regs.s9 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9));
core.regs.s10 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10));
core.regs.s11 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11));
core.regs.t3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3));
core.regs.t4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4));
core.regs.t5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5));
core.regs.t6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6));

fprintf(stream,
" MODE: 0x%lx\n", core.mode);
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2 changes: 1 addition & 1 deletion tools/testing/selftests/kvm/riscv/arch_timer.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -93,7 +93,7 @@ struct kvm_vm *test_vm_create(void)
vcpu_init_vector_tables(vcpus[i]);

/* Initialize guest timer frequency. */
vcpu_get_reg(vcpus[0], RISCV_TIMER_REG(frequency), &timer_freq);
timer_freq = vcpu_get_reg(vcpus[0], RISCV_TIMER_REG(frequency));
sync_global_to_guest(vm, timer_freq);
pr_debug("timer_freq: %lu\n", timer_freq);

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2 changes: 1 addition & 1 deletion tools/testing/selftests/kvm/riscv/ebreak_test.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ int main(void)

TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_DEBUG);

vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc), &pc);
pc = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc));
TEST_ASSERT_EQ(pc, LABEL_ADDRESS(sw_bp_1));

/* skip sw_bp_1 */
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