Merge branch 'srt' into srt

sequencer · Apr 25, 2022 · 63f417a · 63f417a
2 parents 4821208 + c3c3ed1
commit 63f417a
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Showing 3 changed files with 5 additions and 1 deletion.
diff --git a/arithmetic/src/division/srt/OTF.scala b/arithmetic/src/division/srt/OTF.scala
@@ -41,4 +41,5 @@ class OTF(radix: Int, qWidth: Int, ohWidth: Int) extends Module {
 
   output.quotient := Mux(cShiftQ, input.quotient, input.quotientMinusOne)(qWidth-2, 0) ## qIn
   output.quotientMinusOne := Mux(!cShiftQM, input.quotient, input.quotientMinusOne)(qWidth-2, 0) ## qmIn
+
 }
diff --git a/arithmetic/src/division/srt/QDS.scala b/arithmetic/src/division/srt/QDS.scala
@@ -74,4 +74,5 @@ class QDS(rWidth: Int, ohWidth: Int, partialDividerWidth: Int) extends Module {
       BitPat("b00001")
     )
   )
+
 }
diff --git a/arithmetic/src/division/srt/SRT.scala b/arithmetic/src/division/srt/SRT.scala
@@ -4,8 +4,8 @@ import addition.csa.CarrySaveAdder
 import addition.csa.common.CSACompressor3_2
 import utils.extend
 import chisel3._
-import chisel3.util.{log2Ceil, Counter, DecoupledIO, Mux1H, ValidIO}
 
+import chisel3.util.{log2Ceil, Counter, DecoupledIO, Mux1H, ValidIO}
 import scala.math.ceil
 
 /** SRT4
@@ -31,6 +31,7 @@ class SRTOutput(reminderWidth: Int, quotientWidth: Int) extends Bundle {
 
 // only SRT4 currently
 class SRT(
+
   dividendWidth:  Int,
   dividerWidth:   Int,
   n:              Int, // the longest width,
@@ -55,6 +56,7 @@ class SRT(
   val quotient = Reg(UInt(n.W))
   val quotientMinusOne = Reg(UInt(n.W))
   val counter = RegInit(input.bits.counter)
+
   // Control
   // sign of select quotient, true -> negative, false -> positive
   val qdsSign: Bool = Wire(Bool())