$realtobits

Aug 12, 2020 Vivado 2020.1

Using part xc7z020400clg-1 (i.e., the part used on the PYNQ Z1 board)

The purpose of this experiment to check that $realtobits behaves properly in synthesis when `HARD_FLOAT is defined.

The synthesis output matches the expected output (verified by examining the synthesized schematic by hand).

> print(f'0b{svreal.real2recfn(4.56):033b}')
0b010000001000100011110101110000101
> print(f'0b{svreal.real2recfn(-1.23):033b}')
0b110000000000111010111000010100011
> print(f'0b{svreal.real2recfn(1e-15):033b}')
0b001100111000100000001110101111100
> print(f'0b{svreal.real2recfn(-1e15):033b}')
0b110011000111000110101111110101001
>>> print(f'0b{svreal.real2recfn(0):033b}')
0b000000000000000000000000000000000

Test code

`timescale 1ns / 1ps
`define HARD_FLOAT
`include "svreal.sv"

module top (
    `OUTPUT_REAL(a),
    `OUTPUT_REAL(b),
    `OUTPUT_REAL(c),
    `OUTPUT_REAL(d),
    `OUTPUT_REAL(e)
);
    `ASSIGN_CONST_REAL(4.56, a);
    `ASSIGN_CONST_REAL(-1.23, b);
    `ASSIGN_CONST_REAL(1e-15, c);
    `ASSIGN_CONST_REAL(-1e15, d);
    `ASSIGN_CONST_REAL(0, e);
endmodule