uart: put sample points

sigrokproject · Aug 1, 2022 · 6646578 · 6646578
1 parent da0092a
commit 6646578
Showing 1 changed file with 22 additions and 11 deletions.
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
@@ -89,8 +89,9 @@ class ChannelError(Exception):
 class Ann:
     RX_DATA, TX_DATA, RX_START, TX_START, RX_PARITY_OK, TX_PARITY_OK, \
     RX_PARITY_ERR, TX_PARITY_ERR, RX_STOP, TX_STOP, RX_WARN, TX_WARN, \
-    RX_DATA_BIT, TX_DATA_BIT, RX_BREAK, TX_BREAK, RX_PACKET, TX_PACKET = \
-    range(18)
+    RX_DATA_BIT, TX_DATA_BIT, RX_BREAK, TX_BREAK, RX_PACKET, TX_PACKET, \
+    RX_SAMPLES, TX_SAMPLES, \
+        = range(20)
 
 
 class Bin:
@@ -138,6 +139,8 @@ class Decoder(srd.Decoder):
             'values': ('yes', 'no')},
         {'id': 'invert_tx', 'desc': 'Invert TX', 'default': 'no',
             'values': ('yes', 'no')},
+        {'id': 'put_sample_points', 'desc': 'Put sample points', 'default': 'no',
+            'values': ('yes', 'no')},
         {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 50},
         {'id': 'packet_idle_us', 'desc': 'Packet break by idle time, us', 'default': -1},
         {'id': 'rx_packet_delim', 'desc': 'RX packet delimiter (decimal)',
@@ -166,18 +169,22 @@ class Decoder(srd.Decoder):
         ('tx-break', 'TX break'),
         ('rx-packet', 'RX packet'),
         ('tx-packet', 'TX packet'),
+        ('rx-samples', 'RX samples'),
+        ('tx-samples', 'TX samples'),
     )
     annotation_rows = (
         ('rx-data-bits', 'RX bits', (Ann.RX_DATA_BIT,)),
         ('rx-data-vals', 'RX data', (Ann.RX_DATA, Ann.RX_START, Ann.RX_PARITY_OK, Ann.RX_PARITY_ERR, Ann.RX_STOP)),
         ('rx-warnings', 'RX warnings', (Ann.RX_WARN,)),
         ('rx-breaks', 'RX breaks', (Ann.RX_BREAK,)),
         ('rx-packets', 'RX packets', (Ann.RX_PACKET,)),
+        ('rx-samples', 'RX samples', (Ann.RX_SAMPLES,)),
         ('tx-data-bits', 'TX bits', (Ann.TX_DATA_BIT,)),
         ('tx-data-vals', 'TX data', (Ann.TX_DATA, Ann.TX_START, Ann.TX_PARITY_OK, Ann.TX_PARITY_ERR, Ann.TX_STOP)),
         ('tx-warnings', 'TX warnings', (Ann.TX_WARN,)),
         ('tx-breaks', 'TX breaks', (Ann.TX_BREAK,)),
         ('tx-packets', 'TX packets', (Ann.TX_PACKET,)),
+        ('tx-samples', 'TX samples', (Ann.TX_SAMPLES,)),
     )
     binary = (
         ('rx', 'RX dump'),
@@ -199,6 +206,7 @@ def putbinse(self, ss, es, data):
         self.put(ss, es, self.out_binary, data)
 
     def __init__(self):
+        self.put_sample_points = None
         self.bit_width = None
         self.samplerate = None
         self.half_bit_width = None
@@ -238,6 +246,7 @@ def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
         self.stop_bits = float(self.options['stop_bits'])
         self.msb_first = self.options['bit_order'] == 'msb-first'
+        self.put_sample_points = self.options['put_sample_points'] == 'yes'
         self.data_bits = self.options['data_bits']
         self.parity_type = self.options['parity']
         self.bw = (self.data_bits + 7) // 8
@@ -584,18 +593,20 @@ def inspect_sample(self, rxtx, signal, inv):
         # Inspect a sample returned by .wait() for the specified UART line.
         if inv:
             signal = not signal
-
         state = self.state[rxtx]
         if state == State.WAIT_FOR_START_BIT:
             self.wait_for_start_bit(rxtx, signal)
-        elif state == State.GET_START_BIT:
-            self.get_start_bit(rxtx, signal)
-        elif state == State.GET_DATA_BITS:
-            self.get_data_bits(rxtx, signal)
-        elif state == State.GET_PARITY_BIT:
-            self.get_parity_bit(rxtx, signal)
-        elif state == State.GET_STOP_BITS:
-            self.get_stop_bits(rxtx, signal)
+        else:
+            if state == State.GET_START_BIT:
+                self.get_start_bit(rxtx, signal)
+            elif state == State.GET_DATA_BITS:
+                self.get_data_bits(rxtx, signal)
+            elif state == State.GET_PARITY_BIT:
+                self.get_parity_bit(rxtx, signal)
+            elif state == State.GET_STOP_BITS:
+                self.get_stop_bits(rxtx, signal)
+            if self.put_sample_points:
+                self.putgse(self.samplenum, self.samplenum, [Ann.RX_SAMPLES + rxtx, [str(signal)]])
 
     def inspect_edge(self, rxtx, signal, inv):
         # Inspect edges, independently from traffic, to detect break conditions.